CCS/TMS320F28069: Output low for both EPWMxA and EPWMxB at the same time if EPWMxB is Inverted of EPWMxA

Tool/software: Code Composer Studio

I have configured my EPwm1 A and B as inverted. Now I want to have both (A and B) low for some time. With Trip Zone I only manage to have: A and B high, A high and B low, A low and B high. Both low is not possible.

Why?

Is there a better solution to my problem then to change B to normal and afterwards back to inverted?

My Configuration:

EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;           
EPwm1Regs.TBPRD = 37;                            
EPwm1Regs.CMPA.half.CMPA = 19;                   
EPwm1Regs.CMPA.half.CMPAHR = (1 << 8);            
EPwm1Regs.TBPHS.all = 0;                         
EPwm1Regs.TBCTR = 0;                              
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;        
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;    //disable EPWMxSYNCO - Signal
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;           //TBCLK = SYSCLKOUT / (HSPCLKDIV x CLKDIV) (= 90MHz)
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;              //TBCLK = SYSCLKOUT / (HSPCLKDIV x CLKDIV) (= 90MHz)
EPwm1Regs.TBCTL.bit.FREE_SOFT = 11;                //Behaviour of ePWM Time Base Counter in Emulation Mode: Free running
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;       //Load on CTR: Time Base Counter equal to period (TBCTR = TBPRD)
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;        //CMPA-Register writes go to the shadow register
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;                 //Action for Output A when Counter Equals to Period: Set EPWMxA high
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;               //Action for Output A when Counter Equals to CMPA and Counter is incrementing: force EPWMxA to low
EALLOW;
EPwm1Regs.HRCNFG.all = 0x0;                        //Reset the high Resolution Configuration Register
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP;             //Micro-edge Positioner (MEP) controls both edges (CMPAHR and TBPRDHR)
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;             //CMPAHR or TBPRDHR Register controls the edge Position
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD;     //Time Event for loading CMPAHR Shadow to Active Register: Counter = Zero or Counter = PRD
EPwm1Regs.HRCNFG.bit.SELOUTB = HR_INVERT_B;        //EPWMxB Output: is the inverted version of EPWMxA signal
EPwm1Regs.HRCNFG.bit.AUTOCONV = 1;                 //CMPAHR and TBPRDHR are automatically scaled by the HRMSTEP Register (SFO library function)
EPwm1Regs.HRPCTL.bit.HRPE = 1;                     //HRPWM Module can control high resolution of both Duty and Frequency
EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 0;             //Disables Synchronization of high-resolution phase on a SYNCIN, TBCTL(SWFSYNC) or digital Compare Event

//Trip Zone configuration:

EPwm1Regs.TZCTL.bit.TZB = 0x2;
EPwm1Regs.TZCTL.bit.TZA = 0x2;

EDIS;

//Force both low:

EALLOW;

EPwm1Regs.TZFRC.bit.OST = 1;

EDIS;

//Clear force to low:

EALLOW;

EPwm1Regs.TZCLR.bit.OST = 1;

EDIS;

The only solution I found was:

//Force both low:

EALLOW;

EPwm1Regs.HRCNFG.bit.SELOUTB = HR_NORM_B;

EPwm1Regs.TZFRC.bit.OST = 1;

EDIS;

//Clear force to low:

EALLOW;

EPwm1Regs.HRCNFG.bit.SELOUTB = HR_INVERT_B;

EPwm1Regs.TZCLR.bit.OST = 1;

EDIS;