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TMS320C28346: GPxQSELn[GPIO*] bitfields for XINTF

Hideaki Nambu
Mastermind 9165 points
Part Number: TMS320C28346
Other Parts Discussed in Thread: TMS320F28375S,

Hello,

Please let me ask about enabling the C28346 XINTF.
Is it required to write 3=Asynchronous to GPxQSELn[GPIO*] bitfields?
For example, GPAQSEL2[GPIO29] controls qualification of the External Interface Address Line 19.

I could not find such a requirements from the C28346 documents, although the F2837xS TRM requires the GPxQSELy[GPIOz] bitfields to have 3=Asynchronous.

  • 0
    TI__Guru 62975 points

    Hideaki-san,

    I would consider this to be a best practice for XINTF rather than a hard requirement.  The XINTF module operates synchronously with SYSCLK so the default GPIO qualification register value of 0 (1-SYSCLK) should be fine.

    -Tommy

  • 0 in reply to tlee
    Mastermind 9165 points
    Tommy,
    Thank you for your reply.

    At the beginning I should explain its background. You know our thread: e2e.ti.com/.../2505059
    "TMS320F28375S: SDRAM on EMIF2"

    A new finding for the thread was, the EMIF2 max frequency reached 100MHz when the GPxQSELn register bits were changed from zero to three.

    Then I thought that (the value = 0) would be necessary for SDRAM 100MHz operation.
    And here I asked (the value) rewuirement regarding C28346.

    Although, as long as my test (the value = 3) was not necessary for SRAM @100MHz CLK.
  • 0 in reply to Hideaki Nambu
    TI__Guru 62975 points
    Hideaki-san,

    That is an interesting observation about the SDRAM and SRAM operation.

    All of the asynchronous memory (SRAM) timings are based on SYSCLK periods so the SYNC (QSEL=0) should work for most circumstances. The QUAL (QSEL=1,2) settings may have trouble if the R_STROBE duration is very short. ASYNC (QSEL=3) will obviously have the least amount of potential for trouble.

    For SDRAM, the memory interface will manage propagation delay by using the DQM signals to indicate when the data bus is valid. It is possible that the delay introduced by SYNC (QSEL=0) is enough to shift the bus read from a time when the bus is valid to a time when the bus is no longer valid.

    -Tommy
  • 0 in reply to tlee
    Mastermind 9165 points

    Tommy,

    Thank you for your input.

    Let me reconfirm your last paragraph. Do you agree?

    The QSEL=3(Async) might be the best practice for TMS320C28346 to maximize XINTF SDRAM clock frequency.

    -n

  • 0 in reply to Hideaki Nambu
    TI__Guru 62975 points

    Hideaki-san,

    Yes, using QSEL=3 (Async) is best practice for maximizing SRAM operation on XINTF and EMIF.  Note that XINTF does not have SDRAM support.

    For SDRAM on EMIF, I would consider QSEL=3 (Async) to be required in order to maximize the operating frequency.

    -Tommy

  • 0 in reply to tlee
    Mastermind 9165 points
    Tommy,
    Thank you for your clarification. It helps me a lot.