TMS320F28377D: Use high resolution period and high resolution duty cycle simultaneously will cause Jitter on ePWM out

// Disable TBCLKSYNC
    EALLOW;
            SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;     
    EDIS;
 
//Write To CMP, TBPRD, TBPHS registers.
    (*ePWM[j]).TBCTL.bit.PRDLD = TB_SHADOW;             // set Shadow load
    (*ePWM[j]).TBPRD = period;                                         // PWM frequency = 1/(2*TBPRD)
    (*ePWM[j]).CMPA.half.CMPA = period / 2;                   // set duty 50% initially
    (*ePWM[j]).CMPA.half.CMPAHR = (0 << 8);                 // initialize HRPWM extension
    (*ePWM[j]).TBPHS.all = 0;
 
//Configure modes, clock dividers and action qualifier
    (*ePWM[j]).TBCTR = 0;
    (*ePWM[j]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;     // Select up-down count mode
    (*ePWM[j]).TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;      
    (*ePWM[j]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
    (*ePWM[j]).TBCTL.bit.CLKDIV = TB_DIV1;                             // TBCLK = SYSCLKOUT
    (*ePWM[j]).TBCTL.bit.FREE_SOFT = 00;
 
    (*ePWM[j]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;      // LOAD CMPA on CTR = 0
    (*ePWM[j]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;        
    (*ePWM[j]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    (*ePWM[j]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;
 
    (*ePWM[j]).AQCTLA.bit.CAU = AQ_SET;                 
    (*ePWM[j]).AQCTLA.bit.CAD = AQ_CLEAR;
    (*ePWM[j]).AQCTLB.bit.ZRO = AQ_SET
    (*ePWM[j]).AQCTLB.bit.PRD = AQ_CLEAR;
   
//Configure HRPWM registers
    EALLOW;
     (*ePWM[j]).HRCNFG.all = 0x0;
     (*ePWM[j]).HRCNFG.bit.EDGMODE = HR_BEP;                      // MEP control on both edges
     (*ePWM[j]).HRCNFG.bit.CTLMODE = HR_CMP;                      // CMPAHR and TBPRDHR HR control
     (*ePWM[j]).HRCNFG.bit.HRLOAD  = HR_CTR_ZERO_PRD;    // load on CTR = 0 and CTR = TBPRD
     (*ePWM[j]).HRCNFG.bit.AUTOCONV = 1;                               // Enable autoconversion
     (*ePWM[j]).HRPCTL.bit.HRPE = 1;                                         // Turn on high-resolution period control
 
//set TBCTL[PHSEN] = 1
     (*ePWM[j]).TBCTL.bit.PHSEN = 1;
 
//set HRPCTL[TBPHSHRLOADE] = 1
     (*ePWM[j]).HRPCTL.bit.TBPHSHRLOADE = 1;
    
//Do the same to all other PWM modules
…
 
//Enable TBCLKSYNC
     SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;                         
 
//Perform a software sync 
     EPwm1Regs.TBCTL.bit.SWFSYNC = 1;                

{
    Uint16 j;
    //
    // ePWM channel register configuration with HRPWM
    // ePWMxA toggle low/high with MEP control on Rising edge
    //
    // Disable TBCLKSYNC
	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
	EDIS;

    for(j=1; j<PWM_CH; j++)
    {
		//Write To CMP, TBPRD, TBPHS registers.
		(*ePWM[j]).TBCTL.bit.PRDLD = TB_SHADOW;             // set Shadow load
		(*ePWM[j]).TBPRD = period;                                         // PWM frequency = 1/(2*TBPRD)
        (*ePWM[j]).TBPRDHR = (1 << 8);               // PWM frequency = 1/(2*TBPRD)
		(*ePWM[j]).CMPA.bit.CMPA = period/2;                   // set duty 50% initially
		(*ePWM[j]).CMPA.bit.CMPAHR = (1 << 8);                 // initialize HRPWM extension
		(*ePWM[j]).TBPHS.all = 0;

		//Configure modes, clock dividers and action qualifier
		(*ePWM[j]).TBCTR = 0;
		(*ePWM[j]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;     // Select up-down count mode
		(*ePWM[j]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

		(*ePWM[j]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
		(*ePWM[j]).TBCTL.bit.CLKDIV = TB_DIV1;                             // TBCLK = SYSCLKOUT
		(*ePWM[j]).TBCTL.bit.FREE_SOFT = 0x00;

		(*ePWM[j]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;      // LOAD CMPA on CTR = 0
		(*ePWM[j]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
		(*ePWM[j]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
		(*ePWM[j]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;

		(*ePWM[j]).AQCTLA.bit.CAU = AQ_SET;
		(*ePWM[j]).AQCTLA.bit.CAD = AQ_CLEAR;
//		(*ePWM[j]).AQCTLB.bit.ZRO = AQ_SET;
//		(*ePWM[j]).AQCTLB.bit.PRD = AQ_CLEAR;

		//added
		(*ePWM[j]).DBCTL.bit.OUT_MODE = 0x2;//S1=1,S0=1
		(*ePWM[j]).DBCTL.bit.POLSEL = 0x0;//S3=1,S2=0
		(*ePWM[j]).DBCTL.bit.IN_MODE = 0x2;//S5=1,S4=0
		(*ePWM[j]).DBRED.bit.DBRED = 20;//DC_DB_TIME_200NS;

		//Configure HRPWM registers
		EALLOW;
		(*ePWM[j]).HRCNFG.all = 0x0;////
		(*ePWM[j]).HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
		(*ePWM[j]).HRCNFG.bit.CTLMODE = HR_CMP;
		(*ePWM[j]).HRCNFG.bit.EDGMODE = 0x2;//control of both edges (TBPHSHR or TBPRDHR)
		(*ePWM[j]).HRCNFG.bit.AUTOCONV = 1;  // Enable autoconversion
		(*ePWM[j]).HRPCTL.bit.TBPHSHRLOADE = 1;
		(*ePWM[j]).HRPCTL.bit.HRPE=1; // Turn on high-resolution period control.
		EDIS;
    }
		//Enable TBCLKSYNC
	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
	//Perform a software sync
	EPwm1Regs.TBCTL.bit.SWFSYNC = 1;
}