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Pulse Width Modulator (ePWM): Force a Continuous High Synchronously

Other Parts Discussed in Thread: F28M36P63C2, C2000WARE

Hello,

I am trying to understand how to halt the repetition of an EPWMx pulse train output, such that the last pulse is not truncated.  The figure below illustrates the situation.  I'd prefer to use a software command to initiate the halting, such as EPWM1.AQCSFRC.bit.CSFA = 2, which would place the output to a continuous high value, which is what I want.  However, I want the final negative-going pulse to be like all those before it.  In my case, the document sprug04a.pdf applies, and I have studied all the submodules including Dead Band and Trip Zone, but all I can gather from this document is that if the software forcing (CSFA=2) command happens to occur during the negative-going pulse, the pulse width will be truncated accordingly, that is, the forcing action is completely asynchronous to EPWM1 signal.  I searched the community threads on E2E and some of the topics come close to what I am trying to do, but nothing seems conclusive that this is possible.  I am just beginning to use ePWM modules, so perhaps I am missing something.  I would greatly appreciate any suggestions.

Thanks,

Nick

  • Nick,

    Which C2000 device are you using? There's not a straightforward way to do what you're looking for with the ePWM, but I'm pretty sure it can be done.

    What does your trigger event look like? Is it a short pulse or a long event? Is there an expected range?

    Can you explain why you want this to be a software triggered event? Most users prefer for this to be hardware as it is generally a fail event causing the PWM shutdown.


    Regards,
    Kris

  • Hi Kris,

    Thanks for your reply. I am using the F28M36P63C2. The trigger event can be anything really, as it does not relate to any external process state, fail event, or anything like that. It's something I want to purposely set on startup that will serve to "gate" a one-time sync to an external ADC (www.ti.com/.../ads1274.pdf, Fig 73). I'd like the low-going ADC sync pulse to be on the order of 1us in duration at least, but what's equally critical is the timing of the low-to-high edge of the final EPWM pulse, which I am currently controlling using the up-down counter and CAU, PRD settings. This edge must always occur at the PRD, as I show in my diagram, and which is currently running fine.

    But the timing of the final ADC sync pulse (more precisely, the low-to-high edge) needs to be under the control of the C program running in the C28 so as to coordinate with the startup sequence of other peripherals. The trigger event that is needed to turn the EPWM to a continous HIGH value can be as short or as long as necessary, sort of why I tried using EPWM1.AQCSFRC.bit.CSFA = 2, which works, but is asynchronous with the pulse I am trying to gate, and the concern is that there's a chance this could occur in the middle of the sync pulse, thus shifting the low-to-high timing.

    Nick
  • Nick,

    I think I understand most of it, but the "one-time sync" is throwing me off a bit. Is the goal to have the waveform only run for one period, or it runs many times and will terminate after the trigger?

    Could your "trigger" be to just change your CAU to be greater than PRD, therefore it is never reached and the waveform is never set low? Assuming you are using shadow mode, this would result in the current PWM period completing as normal and the following one staying constant high because there is not an AQ event to change it.

    Just a note, the EPWM guide you linked to is for an older device. Use the following document for future reference. It won't make any difference in this scenario, but may help you in other areas. Your EPWM has more features than the F2833x.

    http://www.ti.com/lit/ug/spruhe8d/spruhe8d.pdf

    Regards,
    Kris

  • Hi Kris,

    As far as the ADC is concerned, I only need to generate a single pulse once at startup, so you are correct in that sense, that is, the waveform only needs to run for one period. But since the occurrence of this pulse needs to be synchronous with other peripherals, having several such periods (e.g., 1 or 2 seconds worth) provides a good opportunity to verify that this synchronous condition is met prior to starting data acquisition.

    I have not tried the change the CAU. I will try that. I have not understood how shadow mode works. Do I do anything special or is it enabled by default? The documentation isn't clear. I will check out the newer EPWM guide. Thanks for pointing that out.

    Thank you for your suggestions!

    Nick
  • Hi Nick,

    I'm not sure right off hand if shadow mode is enabled by default, but almost all of the TI examples use it. Take a look at the code available in the "device support" directory of C2000Ware for your device.

    Shadow mode allows for register changes to happen at a predefined point so as to not distort the current PWM switching cycle. In your case, loading CMPA on TBCTR=0 should work well.
  • Kris,

    Updating the CAU and using shadow mode as described above works exactly as I need it to. Problem solved. Thank you very much for your help!

    Nick