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CCS/TMS320F28377S: ePWM synchronization problem using TBCTL[SWFSYNC] Software Forced Synchronization Pulse

jerry chang
Prodigy 70 points
Part Number: TMS320F28377S
Other Parts Discussed in Thread: C2000WARE

Tool/software: Code Composer Studio

Hi Everyone;

I have a problem when I want to synchronize ePWM by using TBCTL.SWFSYNC write 1

The problem is my PWM period is set 4340, it mean the frequency should be 46082Hz (200M/ 4340)

and I found the frequency is very stable(no variation) before enable the synchronization, you can find the picture below:

Then enable the Synchronization(only enable sync, no write 1 to SWFSYNC), the frequency is unstable, variation from 45.87khz to 46.51khz.

My application is want to synchronize between PWM(46080hz) and Timer interrupt(15360hz), but i found once the ePWM sync enable, the frequency is going to unstable.

Here is my PWM Setting

void InitEPWM(void)
{
    EALLOW;
    ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;
    EDIS;

    //
    // enable PWM1, PWM2, PWM3, PWM4, PWM5
    //
    CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM4 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM5 = 1;

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    EDIS;

    InitEPwm1Example();
    InitEPwm2Example();
    InitEPwm3Example();
    InitEPwm4Example();
    InitEPwm5Example();

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
    EDIS;
}

//
// InitEPwm1Example - Initialize EPWM1 configuration
//
void InitEPwm1Example()
{
    // TPWM = (TBPRD + 1) x TTBCL
    EPwm1Regs.TBPRD = 4340;                        // Up Count, = 200M / (15360 x 3) = 4340
    EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;            // Phase is 0
    EPwm1Regs.TBCTR = 0x0000;                    // Clear counter
//    EPwm1Regs.TBSTS.bit.SYNCI = 1;
    //
    // Setup TBCLK
    //
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;        // Up-Down Count
    EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;            // Disable phase loading
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;        // Clock ratio to SYSCLKOUT
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;        // Load registers every ZERO
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm1Regs.CMPA.bit.CMPA = 0;        // 2170 = 50%
    EPwm1Regs.CMPB.bit.CMPB = 0;        // 2170 = 50%

    //
    // Set actions
    //
    EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;

    EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET;
    EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;

    //
    // Active Low PWMs - Setup Deadband
    //
    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;
    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm1Regs.DBRED.bit.DBRED = 0;
    EPwm1Regs.DBFED.bit.DBFED = 0;
}

Any suggestion?

Thanks in advanced.

  • 0
    TI__Genius 10845 points

    Hi,

    Your query has been assigned to the experts. Due to the US Holiday, please expect a reply early next week.

    Thanks

    Vasudha

  • 0 in reply to Vasudha Bhadoria
    TI__Mastermind 24095 points

    Hi,

    Since you are asynchronously forcing SW snchronization w.r.t. the PWM cycle - it could be resulting in sudden change of counter value as you force the sync.
    Can you instead use hardware synchronization?
    Use Counter Zero of EPWM1 as source for synchronization and synchronize other PWMs to this pulse.
    You can also refer to any of the system examples in DigitalPower and MotorControl SDK in C2000ware to learn how the modules are synchronized.
    There is also an example available in base C2000 SW here
    C:\ti\c2000\C2000Ware_2_00_00_02\driverlib\f2837xs\examples\cpu1\epwm\epwm_ex3_synchronization.c

  • 0 in reply to Subrahmanya
    Prodigy 70 points

    Hi Subrahmanya, thanks for your reply.

    I can understand there is some change of PWM counter when i use TBCTL.SWFSYNC to synchronize then the frequency is unstable.

    But I found that  I only set EPwm1Regs.TBSTS.bit.SYNCI = 1 and not to write SWFSYNC, the frequency unstable issue happened.

    Why? Is there any solution?

  • 0 in reply to jerry chang
    TI__Mastermind 24095 points

    Hi,

    Regarding EPwm1Regs.TBSTS.bit.SYNCI
    Reading a 1 on this bit indicates that an external synchronization event has occurred (EPWMxSYNCI). Writing a 1 to this bit will clear the latched event.

    Are you reading a status of 1 and then writing 1 to clear it?

    Also, have you connected any signal to EXTSYNCIN1/2 inputs via InputXbar?
    Please check those connections to see if there is any unintended sync input propagating to the synchronization input.

  • 0 in reply to Subrahmanya
    TI__Mastermind 24095 points

    Hi,

    Is your issue resolved?