TMS320F28377D: EPWM synchronization and software forced synchronization giving incorrect frequecy

Hi all, 

In my practical application, I must need six EPWM channels (EPWM1, EPWM2, EPWM3, EPWM4, EPWM5 and EPWM6) for DC-DC converters. I also have the requirements for phase variation between the modules from -180 to 180 degree.

 For the synchronisation, If I set EPWM1 as master module (by disabling the PHSEN and SYNCOSEL as TB_CTR_ZERO), I get the correct PWM frequency from all module. Since I must have to change the phase shift of the EPWM1 module for the correct functioning, I have to enable the PHSEN and when I do that this generates the wrong frequency.

 There might be a couple of options I am thinking if the microcontroller allow

 (i)      Is there any setting option where EPWM1 can allow phase shift still being a Master module. If possible how can I do that? Can Master module allow phase shift or it should always sit to zero? I was thinking to use software forced synchronisation for EPWM1 and using TB_SYNC_IN to synchronize other five modules. My code setting is given below but this also gives me wrong frequency. Could you please look at it?

(ii)    If this is not possible, can I use EPWM7 as master module for all the above six modules. In this case, how can I establish a sync in between EPWM7 and EPWM1 as I can see from the diagram there is no physical connection between them.

(iii)   If the above two solutions are not possible, how I can set any other EPWM module as Master? Because in my hardware implementation, I already configured EPWM1, EPWM2, EPWM3, EPWM4, EPWM5 and EPWM6 for the three converters.

(iv)    I know the TBPHS value must be positive. Is that correct? If yes then how I can incorporate a positive number for negative phase shift into the TBPHS content?

void configure_pwm1()

{

   EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

   EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;       // Disable phase loading - Master

   EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;     // Clock ratio to SYSCLKOUT

   EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2;

   EPwm1Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count DOWN on sync (=120 deg)

   EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;

   EPwm1Regs.TBCTL.bit. SWFSYNC = 0x1; // forced software synchronisation pulse for PWM module 1

   EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

   }

void configure_pwm2()

{

       EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

   EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;       // // Slave module -Enable phase loading

       EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;     // Clock ratio to SYSCLKOUT

       EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV2;

       EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count DOWN on sync (=120 deg)

       EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;

       EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

}

void configure_pwm3()

{

      EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

       EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;       // Enable phase loading

       EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;     // Clock ratio to SYSCLKOUT

       EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV2;

       EPwm3Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count UP on sync (=240 deg)

       EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;

       EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

       }

void configure_pwm4()

{

   EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

   EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;       // Enable phase loading

   EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;      // Clock ratio to SYSCLKOUT

   EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV2;

   EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count UP on sync (=240 deg)

   EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;

   SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN=0x00; // Select Sync input source for EPWM4 000 selects EPWM1 sync out for mux

}

void configure_pwm5()

{

   EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

   EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE;       // Enable phase loading

   EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;     // Clock ratio to SYSCLKOUT

   EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV2;

   EPwm5Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count UP on sync (=240 deg)

   EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;

   EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

}

void configure_pwm6()

{

   EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

   EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE;       // Enable phase loading

   EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;     // Clock ratio to SYSCLKOUT

   EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV2;

   EPwm6Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count UP on sync (=240 deg)

   EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW;

   EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

   EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;   // Load registers every ZERO

}

Kind regards

Haque