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TMS320F28377D: EPWM synchronization problem with Software forced synchronization scheme giving wrong frequency.

Part Number: TMS320F28377D

Hi all, 

In my practical application, I must need six EPWM channels (EPWM1, EPWM2, EPWM3, EPWM4, EPWM5 and EPWM6) for DC-DC converters. I also have the requirements for phase variation between the modules from -180 to 180 degree.

 For the synchronisation, If I set EPWM1 as master module (by disabling the PHSEN and SYNCOSEL as TB_CTR_ZERO), I get the correct PWM frequency from all module. Since I must have to change the phase shift of the EPWM1 module for the correct functioning, I have to enable the PHSEN and when I do that this generates the wrong frequency.

 There might be a couple of options I am thinking if the microcontroller allow

 (i)      Is there any setting option where EPWM1 can allow phase shift still being a Master module. If possible how can I do that? Can Master module allow phase shift or it should always sit to zero? I was thinking to use software forced synchronisation for EPWM1 and using TB_SYNC_IN to synchronize other five modules. My code setting is given below but this also gives me wrong frequency. Could you please look at it?

 

(ii)    If this is not possible, can I use EPWM7 as master module for all the above six modules. In this case, how can I establish a sync in between EPWM7 and EPWM1 as I can see from the diagram there is no physical connection between them.

(iii)   If the above two solutions are not possible, how I can set any other EPWM module as Master? Because in my hardware implementation, I already configured EPWM1, EPWM2, EPWM3, EPWM4, EPWM5 and EPWM6 for the three converters.

(iv)    I know the TBPHS value must be positive. Is that correct? If yes then how I can incorporate a positive number for negative phase shift into the TBPHS content?

 

 

void configure_pwm1()

{

   EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

   EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;       // Disable phase loading - Master

   EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;     // Clock ratio to SYSCLKOUT

   EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2;

   EPwm1Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count DOWN on sync (=120 deg)

   EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;

   EPwm1Regs.TBCTL.bit. SWFSYNC = 0x1; // forced software synchronisation pulse for PWM module 1

   EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

   }

 

void configure_pwm2()

{

       EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

   EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;       // // Slave module -Enable phase loading

       EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;     // Clock ratio to SYSCLKOUT

       EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV2;

       EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count DOWN on sync (=120 deg)

       EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;

       EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

}

 

void configure_pwm3()

{

      EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

       EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;       // Enable phase loading

       EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;     // Clock ratio to SYSCLKOUT

       EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV2;

       EPwm3Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count UP on sync (=240 deg)

       EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;

       EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

      

       }

 

void configure_pwm4()

{

   EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

   EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;       // Enable phase loading

   EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;      // Clock ratio to SYSCLKOUT

   EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV2;

   EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count UP on sync (=240 deg)

   EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;

   SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN=0x00; // Select Sync input source for EPWM4 000 selects EPWM1 sync out for mux

  

}

 

void configure_pwm5()

{

   EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

   EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE;       // Enable phase loading

   EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;     // Clock ratio to SYSCLKOUT

   EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV2;

   EPwm5Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count UP on sync (=240 deg)

   EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;

   EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

}

 

void configure_pwm6()

{

   EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

   EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE;       // Enable phase loading

   EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;     // Clock ratio to SYSCLKOUT

   EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV2;

   EPwm6Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count UP on sync (=240 deg)

   EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW;

   EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

   EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;   // Load registers every ZERO

}

 

Kind regards

Haque

  • Part Number: TMS320F28377D

    Tool/software: Code Composer Studio

    Hi, 

    I am working on full bridge converter and eventually used three of them to make a three port converter. Each full bridge has two switching legs.

    I would like to generate six PWM signals (for six phase legs) with a variable phase shifts between them on six PWM channels EPWM1,EPWM2,EPWM3,EPWM4,EPWM5,EPWM6 which are connected with hardware. 

    Now I know that one module should set as Master module and rest of those would be slave and sync in signal will flow module 1 to 6. So I set PWM1 module as master and other as slave. 

    My phase logic are as below:

    alpha, beta and gama are in the range +180 to -180 and phi12 and phi13 are in the range of -10 to +10. 

    tbphs1 = -alpha/2;  // phase register 1 value    
    tbphs2 = alpha/2; // phase register 2 value
    tbphs3 = phi12 + (beta/2);  //phase register 3 value
    tbphs4 = phi12 - (beta/2);  //phase register 4 value
    tbphs5 = phi13 + (gama/2);   //phase register 5 value
    tbphs6 = phi13 - (gama/2);   phase register 6 value

    Now using EPWM1 as a master module, I have to set TBPHS =0 and PHSEN=DISABLE but by doing that I am not getting the required phase shift as the value for EPWM1 module is. tbphs1 = -alpha/2;  

    As a result, I used EPWM7 module as master and all other six are as slave. But in this case, the frequency of other signals become incorrect. 

    So what might be the issues with setting up the EPWM modules? Can EPWM7 be master while  EPWM1,EPWM2,EPWM3,EPWM4,EPWM5,EPWM6 are working as slave? Can the phase register values be negative? 

    Can anyone advise me what would the best way to get the variable phase shifted signals ?

    Kind regards,

    Haque

  • Okay to answer your questions at the end,

    No the phase values cannot be negative. You have to do your calculation so that you do not need negative numbers.

    As far as what ePWM can be the master for the rest of the PWMs, you need to look at the PWM SYNC Chain.

    ePWM7 cannot be the master for all of those PWMs.

    Okay now for your application specific questions, can you send me a block diagram that describes what the PWM signals need to be?

  • Hi Nima,

    Thank you for your reply.

    I have uploaded a block diagram specific to my application.

    I am basically using up-down counter to generate the 20 kHz switching signals. I used six PWM signals for six phase legs of the 3 converter. I need to maintain a phase shift between phase legs of each converters and also between the converter to converter. 

    Now I have used PWM1 to PWM6 modules for the six phase legs. 

    If I use PWM 1 as master module that means I need to disable PHSEN register and PWM1 will no longer respond to any phase shift but I need phase changes.

    So I thought that I can use PWM7 module as master and then set PWM1~PWM6 as slave. 

    Can you please look at the block diagram and advise me which should be best configuration of ePWM modules to get the required phase shift?

    Also can I use an equal offset value to avoid any negative values in the phase register? Please let me know if you want to see the code or any further block diagram.

    Regards

    Haque 

  • Hi Nima,

    Could you please look at my queries and get back to me?

    Regards

    Haque

  • Hi all,

    In my practical application, I must need six EPWM channels (EPWM1, EPWM2, EPWM3, EPWM4, EPWM5 and EPWM6) for DC-DC converters. I also have the requirements for phase variation between the modules from -180 to 180 degree.

    For the synchronisation, If I set EPWM1 as master module (by disabling the PHSEN and SYNCOSEL as TB_CTR_ZERO), I get the correct PWM frequency from all module. Since I must have to change the phase shift of the EPWM1 module for the correct functioning, I have to enable the PHSEN and when I do that this generates the wrong frequency.

    There might be a couple of options I am thinking if the microcontroller allow

    (i) Is there any setting option where EPWM1 can allow phase shift still being a Master module. If possible how can I do that? Can Master module allow phase shift or it should always sit to zero? I was thinking to use software forced synchronisation for EPWM1 and using TB_SYNC_IN to synchronize other five modules. My code setting is given below but this also gives me wrong frequency. Could you please look at it?



    (ii) If this is not possible, can I use EPWM7 as master module for all the above six modules. In this case, how can I establish a sync in between EPWM7 and EPWM1 as I can see from the diagram there is no physical connection between them.

    (iii) If the above two solutions are not possible, how I can set any other EPWM module as Master? Because in my hardware implementation, I already configured EPWM1, EPWM2, EPWM3, EPWM4, EPWM5 and EPWM6 for the three converters.

    (iv) I know the TBPHS value must be positive. Is that correct? If yes then how I can incorporate a positive number for negative phase shift into the TBPHS content?





    void configure_pwm1()

    {

    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

    EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading - Master

    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT

    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2;

    EPwm1Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count DOWN on sync (=120 deg)

    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;

    EPwm1Regs.TBCTL.bit. SWFSYNC = 0x1; // forced software synchronisation pulse for PWM module 1

    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

    }



    void configure_pwm2()

    {

    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // // Slave module -Enable phase loading

    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT

    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV2;

    EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count DOWN on sync (=120 deg)

    EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;

    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

    }



    void configure_pwm3()

    {

    EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

    EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading

    EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT

    EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV2;

    EPwm3Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count UP on sync (=240 deg)

    EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;

    EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through



    }



    void configure_pwm4()

    {

    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

    EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading

    EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT

    EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV2;

    EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count UP on sync (=240 deg)

    EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;

    SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN=0x00; // Select Sync input source for EPWM4 000 selects EPWM1 sync out for mux



    }



    void configure_pwm5()

    {

    EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

    EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading

    EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT

    EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV2;

    EPwm5Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count UP on sync (=240 deg)

    EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;

    EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

    }



    void configure_pwm6()

    {

    EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

    EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading

    EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT

    EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV2;

    EPwm6Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count UP on sync (=240 deg)

    EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW;

    EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

    EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO

    }



    Kind regards

    Haque
  • I am putting together the answer. I will get back to you shortly.

  • Hello,

    I had a similar issue recently. If you see a different frequency when changing the duty cycle of EPwm1 then it could be the same as me.

    My issue was that by default the external synchronization signal EXTSYNCIN1 is brought directly to ePWM1 through the INPUT5 signal of the input x-bar. The default selection of INPUT5 is GPIO0, i.e EPWM1A so EPWM1 is actually resynchronizing on itself.

    My workaround was to select an unused GPIO for INPUT5. In my case I chose GPIO95 because I have a 176-pin package where it is unbonded.

    Something like this:

    	__eallow();
    	GpioCtrlRegs.GPCDIR.bit.GPIO95 = 1;
    	GpioDataRegs.GPCCLEAR.bit.GPIO95 = 1;
    	InputXbarRegs.INPUT5SELECT = 95;
    	__edis();

  • Hello Pierre,
    Thanks for your advice. I am keeping duty cycle fixed for all EPWM modules. Your comments really helpful. I wanted to use EPWM7 as Master module due to my hardware limitation for EPWM1 to EPWM6 module. So I am thinking to use EXTSYNCIN1 for EPWM1 coming form EPWM7 though Crossbar. If you read my requirements that I posted previously you will understand more. 

    Any additional comments and suggestions are highly appreciated. 

  • Hi Nima,
    Could you please get back to me with your answer/suggestions? I am really waiting to hear from you to proceed in the next stage of coding. You can also have a look at my code and then suggest me the best.
  • EPWM7 cannot be the master of all EPWMs. 

    So now lets see how we can solve this. First, when you enable Phase shifting PHSEN = 1, when sync occurs, the CTR is loaded with TBPHS. Which if not taken into consideration will mess up all the calculatations. So think about it. when you want to use EPWM1 as master you want it to count from zero to PRD and all others to be phase shifted from the zero of the EPWM1. Now when you enable Phase shift, the counter no longer counts from zero because it gets loaded with TBPHS at sync messing up your calculations.

    The best option would have been using EPWM1 as master (JUST FOR TIME BASE) and EPWM2-7 for your DCDC.

    But that is not a solution now since you already have hardware.

    Also no you cannot use negative values for the TBPHS. This is just an offset that gets loaded in the counter. if you care using Up mode, then a negative phase shift is the same as TBPHS = TBPRD - (absoluteValue[TBPHS value you actually wanted which is negative])

    Now to solve your original problem, you can just add an offset to all you CMPA and CMPB values that you would have used originally. Every time you are doing the caluclations for your CMPA and CMPB for EPWM2-7, take that offset into effect.

    For EPWM 1, on ZERO set EPWM output low, then use CMPA as phase shift, and set at the output at CMPA.

  • I also merged the 2 E2E thread so now we have all the info in one place. I think my answer above should do the trick for your scenario.
  • Hi Nima,

    Thank you very much for your reply with details suggestion. Sorry for the late reply.

    I was able to make EPWM7 as master while EPWM1-6 as slave using the EXTSYNCIN for EPWM1 that comes from EPWM7. It seems work but I need to make sure I am getting the correct phase shift.

    Also since I am using the up-down counter still the equation for negative phase shift will remain same as below

    a negative phase shift is the same as TBPHS = TBPRD - (absoluteValue[TBPHS value you actually wanted which is negative])

    Could you please explain bit more about the last three lines of answers that you have provided? Is it applicable for up-down counter?

    Regards,
    Haque
  • the last three lines of my explanation is for when you use EPWM1 as master. Since you are using EPWM7 and ext sync, you can ignore those lines.
  • If you need to change the phase of PWM1 you should sync. the time base externally, there is an X-bar input 5 /6 that will sync your main time base.
    maybe this resolves your problem. Then only you can enable the phase shift of PWM 1.
    Ashutosh
  • You can not enable the phase for EPWM1 until you got the sync PWM externally. and you asked that PWM7 is my Master sync then it should come from other MCU., not the same MCU.
    maybe this resolves your issue.