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Hello Community,
When I configure the ePWM frequency I obtain the quarter of what I want. It mentioned in the help of Matlab that "For a few TI C2000 processors, there may be a PWM clock divider that divides the SYSCLKOUT to derive the PWM module clock."
My question is How to set this clock if I want receive the same frequancy (configured_Frequency=obtained_Frequency)?
Regards.
Hi,
On this device max frq for ePWM is 100MHz hence. There is a register (PERCLKDIVSEL.EPWMCLKDIV) which is by default set to SYSCLK/2 to provide ePWM clock. It need to be set that way if SYSCLKOUT is greater than 100MHz.
Regards,
Vivek Singh
Hi,
To get a peek in to the configuration could you please attach the model use are working with for both scenario.