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TMS320C28346: Jitter when using internal PLL and impact on HRPM performance

Pawel Piwowarski87949
Intellectual 795 points
Part Number: TMS320C28346

Hi,

we need to select which C28346 part will be best for our application. Our key design priority is to achieve best possible HRPWM parameters and make full use of 55ps resolution. To achieve this we supply an external low-jitter CMOS clock to avoid additional noise and jitter potentially introduced by the internal PLL. But the ext clock CMOS input is limited to 150Mhz while it would be beneficial to use 300Mhz part for our application.

Our question is – can you please estimate what impact on jitter and PWM performance would be if we used the internal PLL to double our external 150 Mhz clock ?

Regards, Pawel

  • 0
    TI__Mastermind 42195 points

    Pawel,

    Helpful details:

    Are you using XCLKIN as you clock source? If so, a clock input of 150MHz is OK.

    Sometimes it can make sense to use a slower input clock so that you can utilize the PLL's clock divider. This can help reduce some of the noise that could have been introduced when multiplying the clock.

    Jitter is typically averaged out over a PWM's width, some clock cycles will be fast and some will be slow averaging out over time. Using a clean clock source will help with the standard "non-HR" portion of the HRPWM but will not affect the MEP size.

    The MEP size will vary with process, temperature and voltage. Increasing the voltage and lowering the temperature will decrease the MEP step size.

    To answer your question:

    The PLL should have a minimal affect on the PWMs performance and no effect on the MEP size.

    Some things you may care about:

    • The MEP size will vary with fluctuation in the device supply voltage(1.2V)
    • The HRPWM output can be affected by varying the loading of the output buffers
    • Each MEP step is not exactly the same size, if you sweep across each element you will see some variation in the step size.

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Intellectual 795 points

    Hi Cody,
    yes, we're using XCLKIN input. We have a configurable clean clock generated with DDS. At this moment
    we have it set to 150MHz, but we can change the frequency to any other value. Even to 300MHz,
    but as we understand XCLKIN accepts only frequences to 150MHz ?
    It is crucial for us what additional jitter is introduced if we use the internal PLL
    to double the XCLKIN clock signal (it w'd be useful to clock the core of the
    processor with a 300MHz clock, but only if it does not degrade the jitter
    performance).
    If it is better (for jitter) to use , for example, 75MHz XCLKIN, and PLL
    to x4 the clock, we can to do that as well. But we must know that it is better 
    than using PLL for doubling (x2).
    There is no information about the internal PLL timing performance in datasheet, that's we are asking
    here.

    Regards, Pawel

  • 0 in reply to Pawel Piwowarski87949
    TI__Mastermind 42195 points

    Pawel,

    Correct the maximum input frequency, when using XCLKIN, is 150MHz.

    We don't provide jitter specifications for the PLL, why are you concerned with such a precise clock? Most applications can accept a reasonable amount of jitter.

    Using the PLL divider can help reduce the jitter introduced my multiplying the PWM. Let's say that when the PLL multiplies the clock it adds XpS of jitter. If you then use a divider of "/2" on the PLL output it will half the frequency and reduce the overall jitter to ~(X/2)pS.

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    TI__Mastermind 42195 points
    I assume this solved your issue, and I will close this thread. If you issue is not resolved feel free to reply here or start a new thread.

    Regards,
    Cody