CCS/TMDSDOCK28335: How to check and resolve, while my program is entering into ILLEGAL_ISR(void) ?

u2k = DCL_runDF22_C2(&controller2, ek);

//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November  1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################

#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
#include "DCL.h"
// #include "F2833x_Device.h"
// #include "F2833x_Examples.h"
// #include "F2833x_GlobalPrototypes.h"
#include "DCLF32.h"
#include "DCL_fdlog.h"

// Prototype statements for functions found within this file.
__interrupt void adc_isr(void);
 void InitEPwm2Example(void);
#define EPWM1_TIMER_TBPRD  1500  // Period register
#define EPWM1_CMPA     1050
//INPUT DATA
#define DATA_LENGTH 1601
#pragma DATA_SECTION(e_array, "PDataLogSection")
float e_array[DATA_LENGTH];
FDLOG eBuf = FDLOG_DEFAULTS;

// full controller results
#pragma DATA_SECTION(u1_array, "QDataLogSection")
float u1_array[DATA_LENGTH];
FDLOG u1Buf = FDLOG_DEFAULTS;

// pre-computed controller results
#pragma DATA_SECTION(u2_array, "RDataLogSection")
float u2_array[DATA_LENGTH];
FDLOG u2Buf = FDLOG_DEFAULTS;

// controller difference data
#pragma DATA_SECTION(d_array, "SDataLogSection")
float d_array[DATA_LENGTH];
FDLOG dBuf = FDLOG_DEFAULTS;

// extern interrupt void control_Isr(void);
__interrupt void adc_isr(void);
// global  variables
long IdleLoopCount = 0;
long IsrCount = 0;
float u1k;
float u2k;
float dk;
float upperLim;
float lowerLim;
uint16_t v;
DCL_DF22 controller1 = DF22_DEFAULTS;
DCL_DF22 controller2 = DF22_DEFAULTS;
int vadc=0;
// FDLOG eBUf = FDLOG_DEFAULTS;
 int out=0;
// Global variables used in this example:
// Uint16 ConversionCount;
float rk = 0.4199f * 4096;
float ek;
float yk;
main()
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.

    InitSysCtrl();
   DINT;
   InitEPwm2Gpio();
    /*.............................ADC_BLOCK..........................*/
   EALLOW;
   #if (CPU_FRQ_150MHZ)     // Default - 150 MHz SYSCLKOUT
     #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3)   = 25.0 MHz
   #endif
   #if (CPU_FRQ_100MHZ)
     #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2)   = 25.0 MHz
   #endif
   EDIS;

   // Define ADCCLK clock frequency ( less than or equal to 25 MHz )
   // Assuming InitSysCtrl() has set SYSCLKOUT to 150 MHz
   EALLOW;
   SysCtrlRegs.HISPCP.all = ADC_MODCLK; // High Speed Periphal clock set to 25 MHz
   EDIS;

// Step 2. Initialize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
   InitGpio();  // Skipped for this example

// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts


// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
   EALLOW;
       SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
      EDIS;
           InitEPwm2Example();
        EALLOW;
       SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
    EDIS;

   InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
   IER = 0x0000;
   IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
   InitPieVectTable();

// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
   EALLOW;  // This is needed to write to EALLOW protected register
   PieVectTable.ADCINT = &adc_isr;
   PieVectTable.TINT0 = &adc_isr;
   EDIS;    // This is needed to disable write to EALLOW protected registers

// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
   InitAdc();  // For this example, init the ADC

// Step 5. User specific code, enable interrupts:

// Enable ADCINT in PIE
   PieCtrlRegs.PIEIER1.bit.INTx6 = 1;
   IER |= M_INT1; // Enable CPU Interrupt 1
   EINT;          // Enable Global interrupt INTM
   ERTM;          // Enable Global realtime interrupt DBGM
   v = 0;
  // Configure ADC
   AdcRegs.ADCTRL1.bit.ACQ_PS = 0x2;
   AdcRegs.ADCTRL1.bit.CPS = 0x1;
   //AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x1;
   AdcRegs.ADCMAXCONV.all = 0x0000;       // Setup 2 conv's on SEQ1
   AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup ADCINA0 as 1st SEQ1 conv.
   //AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup ADCINA1 as 2nd SEQ1 conv.
   AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1
   AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1;  // Enable SEQ1 interrupt (every EOS)
   AdcRegs.ADCTRL3.bit.SMODE_SEL = 1;

// Assumes ePWM1 clock is already enabled in InitSysCtrl();
   EPwm1Regs.ETSEL.bit.SOCAEN = 1;        // Enable SOC on A group
   EPwm1Regs.ETSEL.bit.SOCASEL = 2;       // Select SOC from from CPMA on upcount
   EPwm1Regs.ETPS.bit.SOCAPRD = 1;        // Generate pulse on 1st event
   EPwm1Regs.CMPA.half.CMPA = 0x08FF;     // Set compare A value
   EPwm1Regs.TBPRD = 0x0FFF;              // Set period for ePWM1
   EPwm1Regs.TBCTL.bit.SYNCOSEL = 0x01;
   EPwm1Regs.TBCTL.bit.CTRMODE = 0;       // count up and start

// Wait for ADC interrupt
  /* for(;;)
   {

   } */
   /*............... CONTROLLER SECTION....................*/

   // configure CPU timer 0
    InitCpuTimers();
    ConfigCpuTimer(&CpuTimer0, 90.0, 1.0e+03);

    // initialise data arrays
    DCL_initLog(&eBuf, e_array, DATA_LENGTH);
    DCL_initLog(&u1Buf, u1_array, DATA_LENGTH);
    DCL_initLog(&u2Buf, u2_array, DATA_LENGTH);
    DCL_initLog(&dBuf, d_array, DATA_LENGTH);
    DCL_clearLog(&u1Buf);
    DCL_clearLog(&u2Buf);
    DCL_fillLog(&dBuf, 1.234567f);

    // initialise full controller
    controller1.a1 = -0.5075f;
    controller1.a2 = -0.4925f;
    controller1.b0 = 0.01614f;
    controller1.b1 = 3.84e-5f;
    controller1.b2 = -0.0161f;

    // Initialize Pre-computed controller
    controller2.a1 = controller1.a1;
    controller2.a2 = controller1.a2;
    controller2.b0 = controller1.b0;
    controller2.b1 = controller1.b1;
    controller2.b2 = controller1.b2;

    // clamp limits
    upperLim = 4096.0f;
    lowerLim = 0.0f;

    // enable interrupts
    PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
    IER |= M_INT1;
    EINT;
    StartCpuTimer0();

    // idle loop
    while(1)
    {
        IdleLoopCount++;
    }

} // end of main



__interrupt void  adc_isr(void)
{
     /*.....................................CONTROL BLOCK.............................*/


    // clear timer flag & acknowledge interrupt
        CpuTimer0Regs.TCR.bit.TIF = 1;
        PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

       
              yk = ((float) AdcMirror.ADCRESULT0);
               ek = rk - yk;
            // run pre-computed controller
            u2k = DCL_runDF22_C2(&controller2, ek);

            out = (int) u2k;
            EPwm2Regs.CMPA.half.CMPA = (out) ;
               EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;             // Set PWM1A on Zero
               EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
                EPwm2Regs.AQCTLB.bit.CAU = AQ_SET;       // Set PWM1B on Zero initialize...
               EPwm2Regs.AQCTLB.bit.CAD = AQ_CLEAR;
             // Clear INT flag for this timer
              EPwm2Regs.ETCLR.bit.INT = 1;
              // Acknowledge this interrupt to receive more interrupts from group 3
             PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
            v = DCL_runClamp_C1(&u2k, upperLim, lowerLim);
            if (0 == v)
            {
               DCL_runDF22_C3(&controller2, ek, u2k);
            }

            // store results
            DCL_writeLog(&u1Buf, u1k);
            DCL_writeLog(&u2Buf, u2k);
            DCL_writeLog(&dBuf, dk);
      
        IsrCount++;


 if(IdleLoopCount==0)
 {
  if(v == DATA_LENGTH)
  {
     v = 0;
     IdleLoopCount=1;
  }
  else
  {
      vadc = (AdcRegs.ADCRESULT0 >>4)  ;
        e_array[v]= vadc;
        v++;

  }

  }
  // Reinitialize for next ADC sequence
  AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;         // Reset SEQ1
  AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;       // Clear INT SEQ1 bit
  PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;   // Acknowledge interrupt to PIE
  return;
}

 void InitEPwm2Example()
{
   // Setup TBCLK
   EPwm2Regs.TBPRD = 750;           // Set timer period 801 TBCLKs
   EPwm2Regs.TBPHS.half.TBPHS = 0x0000;           // Phase is 0
   EPwm2Regs.TBCTR = 0x0000;                      // Clear counter

   // Set Compare values
   EPwm2Regs.CMPA.half.CMPA = out;     

   // Setup counter mode
   EPwm2Regs.TBCTL.bit.CTRMODE = 0; // Count up
   EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
   EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
   EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
   EPwm2Regs.TBCTL.bit.SYNCOSEL = 0x00;

   // Setup shadowing
   EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;  // Load on Zero
   EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;


   // Set actions
   EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;             // Set PWM2A on event A, up count
   EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;           // Clear PWM2A on event A, down count
}