CCS/TMS320F28335: f28335 epwm interrupt issue

Jianxiong Li

Part Number: TMS320F28335

Tool/software: Code Composer Studio

Hi,

I am using TMS320F28335, ezdsp platform to generate pwm wave whose duty cycle is determined by output of ADC. And I am using epwm1 interrupt, intending to make the program enter interrupt at every rising edge of pwm wave. My problem is that besides every rising edge, the program also entered the interrupt function every 3.3us, which made me very confused. I tried different configuration of the pwm, but the problem still exist. Can anyone have a look at my code and give some possible causes of the problem? The software environment is CCS 3.3. Any help will be greatly appreciated.

Jianxiong

7801.Main.c

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// DESCRIPTION:
//
//    This example configures ePWM1, ePWM2, ePWM3 to produce an
//    waveform with independant modulation on EPWMxA and
//    EPWMxB.
//
//    The compare values CMPA and CMPB are modified within the ePWM's ISR
//
//    The TB counter is in upmode for this example.
//
//    View the EPWM1A/B, EPWM2A/B and EPWM3A/B waveforms
//    via an oscilloscope
//
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $
// $Release Date: August 4, 2009 $
//###########################################################################
#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
#include "DSP2833x_Device.h" 
#define CollectNum 4
Uint16 Current1, Current2, Current3, Current4, Voltage_in, AdcRes0, AdcRes1, AdcRes2, AdcRes3, AdcRes4, CurrentSum;//, T1, T2, T3, NN;
Uint16 T1 = 252, T2 = 1200, T3 = 216, NN = 20;
Uint16 Start = 1;
//Uint16 CollectNum = 8
Uint16 Voltage_inTemp[CollectNum], Current1Temp[CollectNum];
Uint16 AdcRes[CollectNum];
Uint16 Duty1A, Duty1B, Duty2A, Duty2B, Duty3A, Duty3B, Duty4A, Duty4B;
//int Start = 0;
int N = 20;
int xx, yy;
int Trec = 1;     //, T2rec = 0, T3rec = 0, NNrec = 0;
//Uint16 i;
int ii=0;
//int AdcSocPoint = 0;
Uint16 Pwm1Count = 0;
Uint16 sss = 0;
struct ECAN_REGS ECanaShadow;
// Prototype statements for functions found within this file.
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
void InitEPwm4Example(void);
Uint16 Digi_LPF();
interrupt void epwm1_isr(void);
//interrupt void epwm2_isr(void);
//interrupt void epwm3_isr(void);
//interrupt void epwm4_isr(void);
interrupt void cpu_timer0_isr(void);
interrupt void cpu_timer1_isr(void);
interrupt void cpu_timer2_isr(void);
//interrupt void adc_isr(void);
interrupt void ecan_rec_isr(void);
interrupt void ecan_rec_st_isr(void);
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

// DESCRIPTION:
//
//    This example configures ePWM1, ePWM2, ePWM3 to produce an
//    waveform with independant modulation on EPWMxA and
//    EPWMxB.
//
//    The compare values CMPA and CMPB are modified within the ePWM's ISR
//
//    The TB counter is in upmode for this example.
//
//    View the EPWM1A/B, EPWM2A/B and EPWM3A/B waveforms
//    via an oscilloscope
//
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $
// $Release Date: August 4, 2009 $
//###########################################################################


#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
#include "DSP2833x_Device.h" 

#define CollectNum 4

Uint16 Current1, Current2, Current3, Current4, Voltage_in, AdcRes0, AdcRes1, AdcRes2, AdcRes3, AdcRes4, CurrentSum;//, T1, T2, T3, NN;
Uint16 T1 = 252, T2 = 1200, T3 = 216, NN = 20;
Uint16 Start = 1;
//Uint16 CollectNum = 8
Uint16 Voltage_inTemp[CollectNum], Current1Temp[CollectNum];
Uint16 AdcRes[CollectNum];

Uint16 Duty1A, Duty1B, Duty2A, Duty2B, Duty3A, Duty3B, Duty4A, Duty4B;
//int Start = 0;
int N = 20;
int xx, yy;
int Trec = 1;     //, T2rec = 0, T3rec = 0, NNrec = 0;
//Uint16 i;
int ii=0;

//int AdcSocPoint = 0;
Uint16 Pwm1Count = 0;
Uint16 sss = 0;

struct ECAN_REGS ECanaShadow;

// Prototype statements for functions found within this file.
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
void InitEPwm4Example(void);


Uint16 Digi_LPF();
interrupt void epwm1_isr(void);
//interrupt void epwm2_isr(void);
//interrupt void epwm3_isr(void);
//interrupt void epwm4_isr(void);

interrupt void cpu_timer0_isr(void);
interrupt void cpu_timer1_isr(void);
interrupt void cpu_timer2_isr(void);
//interrupt void adc_isr(void);
interrupt void ecan_rec_isr(void);
interrupt void ecan_rec_st_isr(void);


// Configure the period for each timer
/*#define EPWM1_TIMER_TBPRD  2000  // Period register
#define EPWM1_MAX_CMPA     1950
#define EPWM1_MIN_CMPA       50
#define EPWM1_MAX_CMPB     1950
#define EPWM1_MIN_CMPB       50      */
#if (CPU_FRQ_150MHZ)     // Default - 150 MHz SYSCLKOUT
  #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3)   = 25.0 MHz
#endif
#if (CPU_FRQ_100MHZ)
  #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2)   = 25.0 MHz
#endif
#define ADC_CKPS   0x0   // ADC module clock = HSPCLK/2*ADC_CKPS   = 25.0MHz/(1*2) = 12.5MHz
#define ADC_SHCLK  0xf   // S/H width in ADC module periods                        = 16 ADC clocks
#define AVG        1000  // Average sample limit
#define ZOFFSET    0x00  // Average Zero offset
//#define BUF_SIZE   40    // Sample buffer size

// Global variable for this example

void main(void)
{

//   struct ECAN_REGS ECanaShadow;

//   Uint16 i;
//    Uint16 j;
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
   InitSysCtrl();
 
   EALLOW;
   SysCtrlRegs.HISPCP.all = ADC_MODCLK;	// HSPCLK = SYSCLKOUT/ADC_MODCLK
   EDIS;
// Step 2. Initalize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio();  // Skipped for this example
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the DSP2833x_EPwm.c file
   InitEPwm1Gpio();
   InitEPwm2Gpio();
   InitEPwm3Gpio();
   InitEPwm4Gpio();

   InitECanGpio();

// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
   DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
   InitPieCtrl();
  

// Disable CPU interrupts and clear all CPU interrupt flags:
   IER = 0x0000;
   IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
   InitPieVectTable();
   InitAdc();  
   InitECan();     //eCan mode enabled inside, so ignore SCC-involved configuration. Can clock 75M, bit rate 1M.

// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
   EALLOW;  // This is needed to write to EALLOW protected registers
   PieVectTable.TINT0 = &cpu_timer0_isr;
   PieVectTable.XINT13 = &cpu_timer1_isr;
   PieVectTable.TINT2 = &cpu_timer2_isr;
   PieVectTable.EPWM1_INT = &epwm1_isr;
//   PieVectTable.EPWM2_INT = &epwm2_isr;
//   PieVectTable.EPWM3_INT = &epwm3_isr;
//   PieVectTable.EPWM3_INT = &epwm4_isr;
//   PieVectTable.ADCINT = &adc_isr;
   PieVectTable.ECAN0INTA = &ecan_rec_isr;
   PieVectTable.ECAN1INTA = &ecan_rec_st_isr;

   EDIS;    // This is needed to disable write to EALLOW protected registers


/*   
//receive from PC
   ECanaShadow.CANME.all = ECanaRegs.CANME.all;
   ECanaShadow.CANME.bit.ME20 = 0;
   ECanaShadow.CANME.bit.ME25 = 0;
   ECanaRegs.CANME.all = ECanaShadow.CANME.all;

   EALLOW;
   ECanaShadow.CANGIM.all = ECanaRegs.CANGIM.all;
   ECanaShadow.CANGIM.bit.I0EN = 1;
   ECanaShadow.CANGIM.bit.I1EN = 1;
//   ECanaShadow.CANGIM.bit.GIL = 0;
   ECanaRegs.CANGIM.all = ECanaShadow.CANGIM.all;

   ECanaShadow.CANMIM.all = ECanaRegs.CANMIM.all;
   ECanaShadow.CANMIM.bit.MIM20 = 1;
   ECanaShadow.CANMIM.bit.MIM25 = 1;
   ECanaRegs.CANMIM.all = ECanaShadow.CANMIM.all;
   EDIS;

   ECanaShadow.CANMIL.all = ECanaRegs.CANMIL.all;
   ECanaShadow.CANMIL.bit.MIL20 = 0;
   ECanaShadow.CANMIL.bit.MIL25 = 1;
   ECanaRegs.CANMIL.all = ECanaShadow.CANMIL.all;


   ECanaMboxes.MBOX20.MSGID.all = 0x9FFFF000; 
   ECanaMboxes.MBOX25.MSGID.all = 0x9F000000; 

 


   ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
   ECanaShadow.CANMD.bit.MD20 = 1;              //receive mailbox        
   ECanaShadow.CANMD.bit.MD25 = 1;                                   
   ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

   ECanaShadow.CANOPC.all = ECanaRegs.CANOPC.all;
   ECanaShadow.CANOPC.bit.OPC20 = 1;              //enable overwrite protection       
   ECanaShadow.CANOPC.bit.OPC25 = 0;                             
   ECanaRegs.CANOPC.all = ECanaShadow.CANOPC.all;

   ECanaShadow.CANME.all = ECanaRegs.CANME.all;
   ECanaShadow.CANME.bit.ME20 = 1;
   ECanaShadow.CANME.bit.ME25 = 1;
   ECanaRegs.CANME.all = ECanaShadow.CANME.all;

   ECanaMboxes.MBOX20.MSGCTRL.bit.DLC = 8;
   ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 1;          
*/
   

   IER |= M_INT9;                                      //enable interrupt for can reception
   PieCtrlRegs.PIEIER9.bit.INTx5 = 1;
   PieCtrlRegs.PIEIER9.bit.INTx6 = 1;



   EINT;   // Enable Global interrupt INTM
   ERTM;   // Enable Global realtime interrupt DBGM




   do
   {
      ;
   } while(Trec!=1);    //||(T2rec!=1)||(T3rec!=1)||(NNrec!=1));   // Wait until 4 data are all received from PC  

   InitCpuTimers();   // For this example, only initialize the Cpu Timers

#if (CPU_FRQ_150MHZ)
// Configure CPU-Timer 0, 1, and 2 to interrupt every second:
// 150MHz CPU Freq, 1 second Period (in uSeconds)

   ConfigCpuTimer(&CpuTimer0, 150, T1);    //since actual is 225, change to 275 for accuracy???
   ConfigCpuTimer(&CpuTimer1, 150, T2);
   ConfigCpuTimer(&CpuTimer2, 150, T3);

#endif

#if (CPU_FRQ_100MHZ)
// Configure CPU-Timer 0, 1, and 2 to interrupt every second:
// 100MHz CPU Freq, 1 second Period (in uSeconds)

   ConfigCpuTimer(&CpuTimer0, 100, T1);
   ConfigCpuTimer(&CpuTimer1, 100, T2);
   ConfigCpuTimer(&CpuTimer2, 100, T3);


#endif
//   CpuTimer1Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0

   
   CpuTimer0.InterruptCount = 0;
   CpuTimer1.InterruptCount = 0;
   CpuTimer2.InterruptCount = 0;


// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals();  // Not required for this example

// For this example, only initialize the ePWM

   EALLOW;
   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
   EDIS;

   InitEPwm1Example();
   InitEPwm2Example();
   InitEPwm3Example();
   InitEPwm4Example();

// Wait for ADC interrupt
   EALLOW;
   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
   EDIS;

   IER |= M_INT3;   // Enable CPU INT3 which is connected to EPWM1-3 INT:
   IER |= M_INT1;   // Enable CPU INT1 which is connected to ADCINT and CPUTimer0:
   IER |= M_INT14;  //CPU Timer2
   IER |= M_INT13;
//   IER |= M_INT9;


//   PieCtrlRegs.PIEIER1.bit.INTx6 = 1;      //ADC interruption
   PieCtrlRegs.PIEIER3.bit.INTx1 = 1;          //enable Pwm1 interrupt
   PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
//   PieCtrlRegs.PIEIER9.bit.INTx5 = 1;

   // Enable global Interrupts and higher priority real-time debug events:
   EINT;   // Enable Global interrupt INTM
   ERTM;   // Enable Global realtime interrupt DBGM


// Configure ADC

   AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK;
   AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;     //Freq 12.5MHz
   AdcRegs.ADCTRL1.bit.CONT_RUN = 0;
   AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;
   AdcRegs.ADCTRL3.bit.SMODE_SEL = 0;

   AdcRegs.ADCMAXCONV.all = 0x0000;       // Setup 7 conv's on SEQ1
   AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;     //ADCINA0, first, current 1
//   AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1;     //ADCINB0, current 2
//   AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2;     //ADCINA1, current 3
//   AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3;     //ADCINB1, current 4
//   AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4;     //ADCINA2, voltage in
//   AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5;     //ADCINB2, voltage out
//   AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6;     //ADCINA3, last, temp
   AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1
   AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0;  // Enable SEQ1 interrupt (every EOS)

// Assumes ePWM1 clock is already enabled in InitSysCtrl();     
   EPwm1Regs.ETSEL.bit.SOCAEN = 1;        // Enable SOC on A group
   EPwm1Regs.ETSEL.bit.SOCASEL = 1;       // Select SOC from from CPMA on upcount
   EPwm1Regs.ETPS.bit.SOCAPRD = 1;        // Generate pulse on 1st event        
 
   EPwm1Regs.ETSEL.bit.INTEN = 1;          
   EPwm1Regs.ETSEL.bit.INTSEL = 1;      //IT THIS END OF EVERY PWM???   
   EPwm1Regs.ETPS.bit.INTPRD = 1;        // Generate pulse on 1st event        



   do
   {
      ;
   } while(Start!=1); 
   
EALLOW;   
   GpioCtrlRegs.GPBMUX2.bit.GPIO54=0;
   GpioCtrlRegs.GPBDIR.bit.GPIO54=1;
EDIS;
   GpioDataRegs.GPBDAT.bit.GPIO54=0;
       
   CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0

for(;;)
{
  int jj;

  if(Start == 0)
  {
      EPwm1Regs.CMPA.half.CMPA = 0;   
      EPwm1Regs.CMPB = 0;      

      EPwm2Regs.CMPA.half.CMPA = 0;   
      EPwm2Regs.CMPB = 0;      

      EPwm3Regs.CMPA.half.CMPA = 0;   
      EPwm3Regs.CMPB = 0;      

      EPwm4Regs.CMPA.half.CMPA = 0;   
      EPwm4Regs.CMPB = 0;   

//	  break;      USE CONTINUE?????
  }

  
//     AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1;
   

   for(jj = 0;jj<CollectNum;jj++ )
   {
//       AdcRegs.ADCTRL2.all=0x2000;
//       AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1;

//       while (AdcRegs.ADCST.bit.INT_SEQ1!= 1){}
//       if(ii<CollectNum)
//       {
           Current1Temp[jj] = AdcRegs.ADCRESULT0 >>4;
          // Voltage_inTemp[jj] = AdcRegs.ADCRESULT4 >>4;
 //      }
//       if(ii == CollectNum)
//       {
 //         ii = 0;
//      PieCtrlRegs.PIEIER1.bit.INTx6 = 0;
//       }



  // Reinitialize for next ADC sequence
   AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;         // Reset SEQ1
   AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;       // Clear INT SEQ1 bit
//   PieCtrlRegs.PIEIFR1.bit.INTx6 = 1;

//   PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;   // Acknowledge interrupt to PIE

//       AdcRes[jj] = Voltage_inTemp[jj];          
//       AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0;

   }
   
	
   Current1 = Digi_LPF(Current1Temp);
//   Voltage_in = Digi_LPF(Voltage_inTemp);




//   AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0;



//   Current1 = AdcRegs.ADCRESULT0 >>4;
   Current2 = AdcRegs.ADCRESULT1 >>4;
   Current3 = AdcRegs.ADCRESULT2 >>4;
   Current4 = AdcRegs.ADCRESULT3 >>4;
//   Voltage_in = AdcRegs.ADCRESULT4 >>4;


/*   CurrentSum = Current1 + Current2;
   CurrentSum = CurrentSum + Current3;
   CurrentSum = CurrentSum + Current4;    */


/*
  
   // Write to the MSGID field  

   ECanaMboxes.MBOX0.MSGID.all = 0x9FFFFFFF; // Extended Identifier
   ECanaMboxes.MBOX1.MSGID.all = 0x9FFFFFFE; // Extended Identifier

// Configure Mailbox under test as a Transmit mailbox 

   ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
   ECanaShadow.CANMD.bit.MD0 = 0;
   ECanaShadow.CANMD.bit.MD1 = 0;
   ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

// Enable Mailbox under test 

   ECanaShadow.CANME.all = ECanaRegs.CANME.all;
   ECanaShadow.CANME.bit.ME0 = 1;
   ECanaShadow.CANME.bit.ME1 = 1;
   ECanaRegs.CANME.all = ECanaShadow.CANME.all;


//   EALLOW;
  // ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
   //ECanaShadow.CANMC.bit.DBO = 0;                 //access from LSB instead of MSB
   //ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
   //EDIS;

// Write to DLC field in Master Control reg 

   ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 2;
   ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 2;


// Write to the mailbox RAM field 

   ECanaMboxes.MBOX0.MDH.word.LOW_WORD = 0;
   ECanaMboxes.MBOX0.MDH.word.HI_WORD = Voltage_in;
   ECanaMboxes.MBOX0.MDL.all = 0;

   ECanaMboxes.MBOX1.MDH.word.HI_WORD =Current1;

   ECanaShadow.CANTRS.all = 0;
   ECanaShadow.CANTRS.bit.TRS0 = 1;             // Set TRS for mailbox under test
   ECanaShadow.CANTRS.bit.TRS1 = 1;             // Set TRS for mailbox under test
   ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;


   do
   {
      ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;
   } while(ECanaShadow.CANTA.bit.TA0 == 0 );   // Wait for TA5 bit to be set..


    ECanaShadow.CANTA.all = 0;
    ECanaShadow.CANTA.bit.TA0 = 1;     	         // Clear TA5
    ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;                      

   do
   {
      ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;
   } while(ECanaShadow.CANTA.bit.TA1 == 0 );   // Wait for TA5 bit to be set..


    ECanaShadow.CANTA.all = 0;
    ECanaShadow.CANTA.bit.TA1 = 1;     	         // Clear TA5
    ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;


/



  // Reinitialize for next ADC sequence
//  AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;         // Reset SEQ1
//  AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;       // Clear INT SEQ1 bit
//   PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
  
  
/*  if(Voltage_in>2389)    
  {
        PieCtrlRegs.PIEIER3.bit.INTx1 = 0;                     //disable 4 interrupts
		//PieCtrlRegs.PIEIFR3.bit.INTx1 = 1;
        PieCtrlRegs.PIEIER3.bit.INTx2 = 0;
        PieCtrlRegs.PIEIER3.bit.INTx3 = 0;
        PieCtrlRegs.PIEIER3.bit.INTx4 = 0;      
    //    return;
  }
  else 
  {
        PieCtrlRegs.PIEIER3.bit.INTx1 = 1;                     //disable 4 interrupts
		//PieCtrlRegs.PIEIFR3.bit.INTx1 = 1;
        PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
        PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
        PieCtrlRegs.PIEIER3.bit.INTx4 = 1;      
  //      return;
  }
*/
  


 // CpuTimer0Regs.TCR.all = 0x4421;

  
   if((Current1<1806))//&&(Current2<1806)&&(Current3<1806)&&(Current4<1806))   (Voltage_in<1225)&&
   {
   	  xx = CpuTimer0.InterruptCount - CpuTimer1.InterruptCount;
	  yy = CpuTimer1.InterruptCount - CpuTimer2.InterruptCount;
      if((xx == 0)&&(yy == 0)&&(CpuTimer0.InterruptCount != NN)&&(CpuTimer2Regs.TCR.bit.TSS == 1))   //TSS: prevent mistake caused by entering timer interrupt after executing previous sentence
	  {

     //   do
//   {
//      ;
//   } while(PieCtrlRegs.PIEIFR3.bit.INTx1 == 1);
         if(sss == 0)//&&(CpuTimer0.InterruptCount < NN))
         {
            Duty1A = 200; 
 	        Duty1B = 0;
            PieCtrlRegs.PIEIFR3.bit.INTx1 = 1;                   
         }
         else if(sss == 1)//&&(CpuTimer0.InterruptCount < NN))
         {
            Duty1A = 850;   
 	        Duty1B = 0;       
            PieCtrlRegs.PIEIFR3.bit.INTx1 = 1;              
         }
         else 
         {
//          EPwm1Regs.ETSEL.bit.INTEN = 0;          
//          PieCtrlRegs.PIEIER3.bit.INTx1 = 0;          //disable Pwm1 interrupt  
            PieCtrlRegs.PIEIFR3.bit.INTx1 = 1;        //NECESSARY???

//     CpuTimer0Regs.TCR.bit.TSS = 0; // Use write-only instruction to set TSS bit = 0
//     CpuTimer0Regs.TCR.all = 0x4421; 

            if(Current1>400)    
            {
                 Duty1A = 0;
	             Duty1B = 0;
            }
            else if(Current1<350)
            {
                 Duty1A = 465;
		         Duty1B = 0;
            }
            else 
            {
	    	 ;
            }
      
                
            if(Current2>602)    
           {
                  Duty2A = 0;
		         Duty2B = 0;
            }
            else if(Current2<400)
            {
                 Duty2A = 0;
		         Duty2B = 0;
            }
            else 
            {
	    	 ;
            }
        
            
            if(Current3>602)    
            {
                 Duty3A = 0;
		         Duty3B = 0;
            }
            else if(Current3<400)
            {
                 Duty3A = 0;
       	         Duty3B = 0;
            }
            else 
            {
	    	 ;
            }

        
            if(Current4>602)    
            {
                 Duty4A = 0;
		         Duty4B = 0;
            }
            else if(Current4<400)
           {
                  Duty4A = 0;
		         Duty4B = 0;
            }
            else 
            {
	    	 ;
            }

	     }
      }
	  else if((xx == 1)&&(yy == 0)&&(CpuTimer0Regs.TCR.bit.TSS == 1))
	  {
      //  CpuTimer0Regs.TCR.all = 0x0411; 
	       Duty1A = 0;
	       Duty1B = 900; //930;
           Duty2A = 0;
	       Duty2B = 0; //930;
           Duty3A = 0;
	       Duty3B = 0; //930;
           Duty4A = 0;
	       Duty4B = 0; //930;    
	  }

	  else if((xx == 0)&&(yy == 1)&&(CpuTimer1Regs.TCR.bit.TSS == 1))
      {
      //  CpuTimer0Regs.TCR.all = 0x0411; 
		   Duty1A = 0;
	       Duty1B = 0;
           Duty2A = 0;
	       Duty2B = 0;
           Duty3A = 0;
	       Duty3B = 0;
           Duty4A = 0;
	       Duty4B = 0;
	  }
   

   }
   else
   {
         Duty1A = 0;
	     Duty1B = 0;
         Duty2A = 0;
	     Duty2B = 0;
         Duty3A = 0;
	     Duty3B = 0;
         Duty4A = 0;
	     Duty4B = 0;
 //     break;
   }

   EPwm1Regs.CMPA.half.CMPA = Duty1A;   
   EPwm1Regs.CMPB = Duty1B;      

   EPwm2Regs.CMPA.half.CMPA = Duty2A;   
   EPwm2Regs.CMPB = Duty2B;      

   EPwm3Regs.CMPA.half.CMPA = Duty3A;   
   EPwm3Regs.CMPB = Duty3B;      

   EPwm4Regs.CMPA.half.CMPA = Duty4A;   
   EPwm4Regs.CMPB = Duty4B;   

//   do
//   {
//      ;
//   } while(PieCtrlRegs.PIEIFR3.bit.INTx1 == 1); 

}



}


interrupt void ecan_rec_isr(void)
{
   unsigned int mailbox_nr;
   mailbox_nr = ECanaRegs.CANGIF0.bit.MIV0;
   if(mailbox_nr == 20)
   {
      do
      {
         ECanaShadow.CANRMP.all = ECanaRegs.CANRMP.all;
      } while(ECanaShadow.CANRMP.bit.RMP20 == 0 );   // Wait for RPM bit to be set..   

      ECanaShadow.CANRMP.bit.RMP20 = 0;
      ECanaRegs.CANRMP.all = ECanaShadow.CANRMP.all;

      T1 = ECanaMboxes.MBOX20.MDH.word.HI_WORD;
      T2 = ECanaMboxes.MBOX20.MDH.word.LOW_WORD;
      T3 = ECanaMboxes.MBOX20.MDL.word.HI_WORD;
      NN = ECanaMboxes.MBOX20.MDL.word.LOW_WORD;

      Trec = 1;

   
   }

   PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;   // Acknowledge interrupt to PIE

}


interrupt void ecan_rec_st_isr(void)
{
   unsigned int mailbox_nr2;
   mailbox_nr2 = ECanaRegs.CANGIF1.bit.MIV1;
   if(mailbox_nr2 == 25)
   {
      do
      {
         ECanaShadow.CANRMP.all = ECanaRegs.CANRMP.all;
      } while(ECanaShadow.CANRMP.bit.RMP25 == 0 );   // Wait for RPM bit to be set..   

      ECanaShadow.CANRMP.bit.RMP25 = 0;
      ECanaRegs.CANRMP.all = ECanaShadow.CANRMP.all;

      Start = ECanaMboxes.MBOX25.MDH.byte.BYTE4;
      PieCtrlRegs.PIEIFR9.bit.INTx6 = 1;
   }
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;   // Acknowledge interrupt to PIE

}







interrupt void cpu_timer0_isr(void)
{
 //  CpuTimer0.InterruptCount++;
 
 
  // CpuTimer0Regs.TCR.bit.TSS = 1; // Use write-only instruction to set TSS bit = 0
   if(CpuTimer0.InterruptCount < NN) 
  {
   CpuTimer0.InterruptCount++;
   CpuTimer0Regs.TCR.bit.TSS = 1; // Use write-only instruction to set TSS bit = 0
   CpuTimer0Regs.TCR.bit.TIE = 0; // Use write-only instruction to set TSS bit = 0
  
   CpuTimer1Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0

  }
//  else
//  {
//    CpuTimer0.InterruptCount=1;
//  }
   //EPwm1Regs.CMPA.half.CMPA = 0;
   //EPwm1Regs.CMPB = 0;


   // Acknowledge this interrupt to receive more interrupts from group 1
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;


}




interrupt void cpu_timer1_isr(void)
{ 
 
  // CpuTimer0Regs.TCR.bit.TSS = 1; // Use write-only instruction to set TSS bit = 0
   if(CpuTimer1.InterruptCount < NN)
  {
     CpuTimer1.InterruptCount++;
     CpuTimer1Regs.TCR.bit.TSS = 1; // Use write-only instruction to set TSS bit = 0
     CpuTimer1Regs.TCR.bit.TIE = 0; // Use write-only instruction to set TSS bit = 0

     CpuTimer2Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
  
   }
   // Acknowledge this interrupt to receive more interrupts from group 1
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

}


interrupt void cpu_timer2_isr(void)
{ 
 
  // CpuTimer0Regs.TCR.bit.TSS = 1; // Use write-only instruction to set TSS bit = 0
  if(CpuTimer2.InterruptCount < NN)
  {
     CpuTimer2Regs.TCR.bit.TSS = 1; // Use write-only instruction to set TSS bit = 0
     CpuTimer2Regs.TCR.bit.TIE = 0; // Use write-only instruction to set TSS bit = 0


     if(CpuTimer2.InterruptCount < NN-1)
	 {
	    sss = 0;
        Pwm1Count = 0;
        EPwm1Regs.ETSEL.bit.INTEN = 1;          
        PieCtrlRegs.PIEIER3.bit.INTx1 = 1;          //enable Pwm1 interrupt  
//     PieCtrlRegs.PIEIFR3.bit.INTx1 = 1;      
        CpuTimer2.InterruptCount++;

     }
	 else 
	 {
        EPwm1Regs.ETSEL.bit.INTEN = 0;          
        PieCtrlRegs.PIEIER3.bit.INTx1 = 0;          //enable Pwm1 interrupt  
        CpuTimer2.InterruptCount++;
        
	 }
     CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0


  
  }
  else if(CpuTimer2.InterruptCount == NN)          //IntCnt=2
  {
     CpuTimer0Regs.TCR.bit.TSS = 1; // Use write-only instruction to set TSS bit = 0
     CpuTimer0Regs.TCR.bit.TIE = 0; // Use write-only instruction to set TSS bit = 0
     CpuTimer1Regs.TCR.bit.TSS = 1; // Use write-only instruction to set TSS bit = 0
     CpuTimer1Regs.TCR.bit.TIE = 0; // Use write-only instruction to set TSS bit = 0
     CpuTimer2Regs.TCR.bit.TSS = 1; // Use write-only instruction to set TSS bit = 0
     CpuTimer2Regs.TCR.bit.TIE = 0; // Use write-only instruction to set TSS bit = 0

  }
   // Acknowledge this interrupt to receive more interrupts from group 1
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

}





/*

// ADC conversion results   
interrupt void adc_isr(void)
{
//  int ii = 0;
//   Current1 = AdcRegs.ADCRESULT0 >>4;
//   Current2 = AdcRegs.ADCRESULT1 >>4;
//   Current3 = AdcRegs.ADCRESULT2 >>4;
//   Current4 = AdcRegs.ADCRESULT3 >>4;
//   Voltage_in = AdcRegs.ADCRESULT4 >>4;

   if(ii<CollectNum)
   {
      Voltage_inTemp[ii] = AdcRegs.ADCRESULT4 >>4;
      ii++;
   }
   if(ii == CollectNum)
   {
      ii = 0;
//      PieCtrlRegs.PIEIER1.bit.INTx6 = 0;
   }

  // Reinitialize for next ADC sequence
  AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;         // Reset SEQ1
  AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;       // Clear INT SEQ1 bit
   PieCtrlRegs.PIEIFR1.bit.INTx6 = 1;

   PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;   // Acknowledge interrupt to PIE

//   return;
}
*/

                           
                                      
interrupt void epwm1_isr(void)
{
GpioDataRegs.GPBDAT.bit.GPIO54=1;
   
//   EPwm1Regs.TBCTR=Current1;

   // Clear INT flag for this timer
   EPwm1Regs.ETCLR.bit.INT = 1;

//   PieCtrlRegs.PIEIFR3.bit.INTx1 = 0;      

   // Acknowledge this interrupt to receive more interrupts from group 3
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

   Pwm1Count++;
   sss=Pwm1Count/2;
GpioDataRegs.GPBDAT.bit.GPIO54=0;
}

/*
interrupt void epwm2_isr(void)
{

   EPwm2Regs.TBCTR=Current2;

   // Clear INT flag for this timer
   EPwm2Regs.ETCLR.bit.INT = 1;

   // Acknowledge this interrupt to receive more interrupts from group 3
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

interrupt void epwm3_isr(void)
{

   EPwm3Regs.TBCTR=Current3;

   // Clear INT flag for this timer
   EPwm3Regs.ETCLR.bit.INT = 1;

   // Acknowledge this interrupt to receive more interrupts from group 3
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

interrupt void epwm4_isr(void)
{

   EPwm4Regs.TBCTR=Current4;

   // Clear INT flag for this timer
   EPwm4Regs.ETCLR.bit.INT = 1;

   // Acknowledge this interrupt to receive more interrupts from group 3
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}          */

void InitEPwm1Example()
{

   // Setup TBCLK
   EPwm1Regs.TBCTL.bit.CTRMODE = 0x10; // stop counting
   EPwm1Regs.TBPRD = 900;       // Set timer period
   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Disable phase loading
   EPwm1Regs.TBPHS.half.TBPHS = 0x0000;       // Phase is 0
   EPwm1Regs.TBCTR = 0x0000;                  // Clear counter
   EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
   EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

   // Setup shadow register load on ZERO
   EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

   // Set Compare values
   EPwm1Regs.CMPA.half.CMPA = 0;    
   EPwm1Regs.CMPB = 0;             

   // Set actions
   EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;            // Set PWM1A on Zero
   EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;          // Clear PWM1A on event A, up count

//   EPwm1Regs.AQCTLA.bit.CBD = AQ_SET;           
   EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET;            // Set PWM1A on Zero
   EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;          // Clear PWM1A on event A, up count

   // Interrupt where we will change the Compare Values
//   EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
//   EPwm1Regs.ETSEL.bit.INTEN = 1;                // Enable INT
   EPwm1Regs.ETSEL.bit.SOCAEN = 1;        // Enable SOC on A group
   EPwm1Regs.ETSEL.bit.SOCASEL = 1;       // Select SOC from from CPMA on upcount
}


void InitEPwm2Example()
{
   // Setup TBCLK
   EPwm2Regs.TBCTL.bit.CTRMODE = 0x10; // Count up
   EPwm2Regs.TBPRD = 930;       // Set timer period
   EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Disable phase loading
   EPwm2Regs.TBPHS.half.TBPHS = 0x0000;       // Phase is 0
   EPwm2Regs.TBCTR = 0x0000;                  // Clear counter
   EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
   EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

   // Setup shadow register load on ZERO
   EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

   // Set Compare values
   EPwm2Regs.CMPA.half.CMPA = 0;    
   EPwm2Regs.CMPB = 0;             

   // Set actions
   EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET;            // Set PWM1A on Zero
   EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;          // Clear PWM1A on event A, up count
   EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET;           
   EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR;
   // Interrupt where we will change the Compare Values
   EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
   EPwm2Regs.ETSEL.bit.INTEN = 1;                // Enable INT
   EPwm2Regs.ETSEL.bit.SOCAEN = 1;        // Enable SOC on A group
   EPwm2Regs.ETSEL.bit.SOCASEL = 1;       // Select SOC from from CPMA on upcount

}

void InitEPwm3Example(void)
{

   // Setup TBCLK
   EPwm3Regs.TBCTL.bit.CTRMODE = 0x10; // Count up
   EPwm3Regs.TBPRD = 930;       // Set timer period
   EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Disable phase loading
   EPwm3Regs.TBPHS.half.TBPHS = 0x0000;       // Phase is 0
   EPwm3Regs.TBCTR = 0x0000;                  // Clear counter
   EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
   EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;

   // Setup shadow register load on ZERO
   EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

   // Set Compare values
   EPwm3Regs.CMPA.half.CMPA = 0;    
   EPwm3Regs.CMPB = 0;             

   // Set actions
   EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET;            // Set PWM1A on Zero
   EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;          // Clear PWM1A on event A, up count
   EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;           
   EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR;  
   // Interrupt where we will change the Compare Values
   EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
   EPwm3Regs.ETSEL.bit.INTEN = 1;                // Enable INT
   EPwm3Regs.ETSEL.bit.SOCAEN = 1;        // Enable SOC on A group
   EPwm3Regs.ETSEL.bit.SOCASEL = 1;       // Select SOC from from CPMA on upcount
}


void InitEPwm4Example(void)
{

   // Setup TBCLK
   EPwm4Regs.TBCTL.bit.CTRMODE = 0x10; // Count up
   EPwm4Regs.TBPRD = 930;       // Set timer period
   EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Disable phase loading
   EPwm4Regs.TBPHS.half.TBPHS = 0x0000;       // Phase is 0
   EPwm4Regs.TBCTR = 0x0000;                  // Clear counter
   EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
   EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;

   // Setup shadow register load on ZERO
   EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

   // Set Compare values
   EPwm4Regs.CMPA.half.CMPA = 0;    
   EPwm4Regs.CMPB = 0;             

   // Set actions
   EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET;            // Set PWM1A on Zero
   EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;          // Clear PWM1A on event A, up count
   EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET;           
   EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR;          

   // Interrupt where we will change the Compare Values
   EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
   EPwm4Regs.ETSEL.bit.INTEN = 1;                // Enable INT
   EPwm4Regs.ETSEL.bit.SOCAEN = 1;        // Enable SOC on A group
   EPwm4Regs.ETSEL.bit.SOCASEL = 1;       // Select SOC from from CPMA on upcount
}


Uint16 Digi_LPF(Uint16 AdcRes[4])
{
   int j;
   Uint32 SumTemp = 0;
   for(j=0; j<CollectNum; j++)
   {
      SumTemp = SumTemp + AdcRes[j];
//	  DELAY_US(1);
   }
   
   return (Uint16)(SumTemp/4);   //for CollectNum = 8
}
//===========================================================================
// No more.
//===========================================================================

over 7 years ago

0 Devin Cottier over 7 years ago

TI__Guru 60865 points

Hi Jianxiong,

The code enters the ePWM ISR spuriously every 3.3us? This is the same ISR that is correctly being entered every ePWM cycle?

What methods are you using to determine the ISR is entered? Are you looking at GPIO54 and seeing an extra toggle on a scope capture?

My best guess is that this has something to do with

"PieCtrlRegs.PIEIFR3.bit.INTx1 = 1; //NECESSARY???"

setting the ISR flag via SW and causing the ISR to be entered.

p.s.

CCS3.3 and ezDSP is some pretty old HW/SW. If you are starting a new project I think you can get CCSv8 for free and I think that should work OK with F28335. We also now have much lower cost EVMs for newer devices e.g. F28379D launchpad XL
(F28335 is still a great device for new development though if you need a really fast ADC)

0 Jianxiong Li over 7 years ago in reply to Devin Cottier

Prodigy 20 points

Hi Devin! I fixed the problem. It is indeed related to PIEIFR register, I removed it and also modified some order of initialization, then the interrupt works.

Personally I tend to use newer HW/SW, but this time it was chosen by the leader of my group. I will tried to use newer ones in the future.

Thanks for your help.

Jianxiong

C2000™︎ microcontrollers

C2000 microcontrollers forum

CCS/TMS320F28335: f28335 epwm interrupt issue