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TMS320F28335: Question about ePWM of DSP F28335

fei xiao
Prodigy 80 points
Part Number: TMS320F28335

Hello!

I have one question that puzzled me for a long time ， about EPWM:

As shown above, high level means ADC ISR, if I update PWM register value Every cycle in this ADC ISR, and I use PWM compare shadow register,  C code is like this:

interrupt void ADCISR(void)

{

    ....

    EPwm1Regs.CMPA.half.CMPA = a1;
    EPwm4Regs.CMPA.half.CMPA = a2;
    EPwm2Regs.CMPA.half.CMPA = b1;            //<------------------------
    EPwm5Regs.CMPA.half.CMPA = b2;
    EPwm3Regs.CMPA.half.CMPA = c1;
    EPwm6Regs.CMPA.half.CMPA = c2;

    ...

}

As you see, ADC ISR should be strictly executed once at 50us, but because freemodbus closed the global interrupt when processing a frame of data, the ADC ISR was delayed. As shown in the red box.

So, In this case, is there such a possibility: when  DSP  Finished  "EPwm2Regs.CMPA.half.CMPA = b1;" ,  PWM transfers the values of all shadow registers to the PWM action registers, which causes the value of "EPwm2Regs.CMPA.half.CMPA" to be the result of a new cycle calculation, while the value of "EPwm5Regs.CMPA.half.CMPA" is still the previous cycle result of the calculation. If these two PWMs control the upper and lower tubes of the same bridge , is there a possibility that the upper and lower bridge are directly connected?

  • 0
    TI__Mastermind 22810 points

    Hi Fei,

    It sounds like there are two separate concerns here, one that the ADC ISR is being delayed and secondly that the ISR will not fully execute? Am I correct in this?

    fei xiao said:
    when  DSP  Finished  "EPwm2Regs.CMPA.half.CMPA = b1;" ,  PWM transfers the values of all shadow registers to the PWM action registers, which causes the value of "EPwm2Regs.CMPA.half.CMPA" to be the result of a new cycle calculation, while the value of "EPwm5Regs.CMPA.half.CMPA" is still the previous cycle result of the calculation.

    Once the ISR is entered it will complete before moving on to another task. I don't see why the program would stop right after the write to EPWM2. The ADC ISR getting delayed will not affect what occurs within the ISR. Can you please elaborate on the comment made above?

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Prodigy 80 points

    Hi!

    when  DSP  Finished  "EPwm2Regs.CMPA.half.CMPA = b1;" ,  PWM transfers the values of all shadow registers to the PWM action registers, which causes the value of "EPwm2Regs.CMPA.half.CMPA" to be the result of a new cycle calculation, while the value of "EPwm5Regs.CMPA.half.CMPA" is still the previous cycle result of the calculation.

    In my opinion, "PWM transfers the values of all shadow registers to the PWM action registers" is hardware action(which actions when the PWM  count is equal to 0 ), It can be performed at the same time as the software action (write to EPWM2). Is a parallel action.

    So, this hardware action can occurs at any time during the execution of the ADC ISR!

    Did I understand it wrong?

  • 0 in reply to fei xiao
    TI__Mastermind 22810 points

    Hi fei,

    If you have shadow mode enabled for CMPA that means that any writes to the CMPA register will not be transferred into the active register until the load mode condition occurs (in your case at a ZRO event). Within your ADC ISR, you write new CMPA values to EPWM1, EPWM2, EPWM3, EPWM4, EPWM5, and EPWM6. These new values will not be transferred into the active registers until a ZRO event occurs.

    Now, there is a possibility that since the ADC ISR and the EPWM waveform are not synchronized that during your ADC ISR a ZRO event occurs for one or all of your EPWM modules. This could cause some of the EPWM modules to have the updated CMPA values while the other modules may not. In order to avoid this, I would suggest the following:

    Create an EPWM ISR that executes a know good point within the EPWM cycle (for example at a ZRO event).Then within the EPWM ISR you can write the new CMPA values that you've calculated. These new CMPA values will not be transferred into the active registers until the next ZRO event but this way you don't run the risk of updating only some of the EPWM modules and not the others. This method assumes that the interested modules (EPWM 2/5) are configured with the same period and phase. 

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Prodigy 80 points

    Hi,

    It seems that this does not fundamentally solve the problem.
    The reason why ADC ISR has been delayed and not synchronized with PWM is because I use FreeModbus. When FreeModbus processing a frame of communication data, DINT will be used to close all interrupts, and EINT will open all interrupts when the processing is completed.
    If this is the case, even if the PWM ISR is turned on, will the PWM ISR be delayed and it is not synchronized with the PWM cycle?

  • 0 in reply to fei xiao
    TI__Mastermind 22810 points

    Hi fei,

    Can you please describe how EPWM 2/5 are configured? If they have the same period then the shadow to active load for EPWM 2 and 5 will occur at the same time. This minimizes the risk of any mismatch between the two compare values. Even if DINT is setup, if an ISR is currently executing it should still finish its task. 

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Prodigy 80 points

    Hi  Marlyn Rosales Castaneda20, 

    EPWM 2/5 are configured sync with PWM1, so they are Sync count.

    The point is writing to  PWM2/5 should be active in a safe time(if the ADC ISR is not disturbed), but now it active when the shadow to active load for EPWM 2/5(with small probability).

    Thanks so much!

  • 0 in reply to fei xiao
    TI__Mastermind 22810 points

    Hi Fei,

    I am not very familiar with FreeModBus, but do you have the capability to know when DINT will be set (ie. when you have a frame of communication about to be processed)? If you can set a variable to reflect this you could check that variable within your ISR (If DINT was not set then there was no delay so write to the CMPA registers. If it was set then do not write the new values to the CMPA registers so that EPWM 2 and EPWM5 retain the same values from the previous time until the ISR is within the time frame you want.)

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Prodigy 80 points

    Hi,

    It seems that there are other better solutions, I will try your method.