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TMS320F28075: Abnormal behavior of using CMPSS to trip the ePWM on a cycle-by-cycle basis

Part Number: TMS320F28075

One of my important customer is designing digital power module using F28075. Now during their debugging, they found the power module(half-bridge) would be damaged because of short through. And they found the damage came from the complementary ePWM output signal was changed accidentally. 

ePWM1A and ePWM1B were configured to complementary output. Ext SyncIn was connected to ePWM1A. CMPSS was used to trip the ePWM1 on a cycle-by-cycle basis. You can find the ePWM output waveforms they found. In the third waveform, ePWM1B cannot be cleared.

You can find their scope capture as follows. The purple waveform(CH3) in the first picture is ePWM1A, and the purple waveform(CH3) in the second picture is ePWM1B.

And there is no ePWM configuration again except the configuration(attached also) during initialization.

Drv_PWM.cpp

Drv_PWM.h

Would you kindly help to check the root cause of this issue?

Thanks.

Regards,

Young Hu

  • Hi,

    You said that "CMPSS was used to trip the ePWM1 on a cycle-by-cycle basis".
    Is this behavior observed on every comparator trip or does this happen only once in a while?
    Also, the unexpected behavior seems to be occurring after the trip is cleared at period match event.
    Are you changing any PWM configuration during run time or when the trip occurred?
  • Hi Bharathi,

    I am inviting customer to explain directly. And this behavior in not happened on every trip, just accidently. And there is no changing PWM configuration during run time.

    Thanks.

    Regards,

    Young

  • Ok. Will wait for customer response.
    As I said earlier, unexpected behavior seems to be occurring after the trip is cleared at period match event. So, it may or may not be related to the trip.
  • Hi Bharathi,

            First of all, thank you very much for your attention to this issue. I will answer a few questions.

            Question1: Is this behavior observed on every comparator trip or does this happen only once in a while?

            Reply:  It happen only once in a while. It has appeared many times that CMPSS trip the ePWM1 on a cycle-by-cycle basis before it damaged, and ePWM1A and ePWM1B are complementary output.

            Question2: Are you changing any PWM configuration during run time or when the trip occurred?

            Reply: PWM configuration is only configured at initialization. PWM configuration is not changed during run time.

             At present, we find the following phenomena.

    1. ePWMxA and ePWMxB are configured as two independent input sources in previous procedures based on f28075 datasheet. 

    That is, EPwm1Regs.DBCTL.bit.IN_MODE = 0x2; 

    10: EPWMxA In (from the action-qualifier) is the source for risingedgedelayed signal.EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal.

    So we assign values to CMPA and CMPB respectively in the last part of CLA, but they are executed one by one.

    Such as:

      EPwm1Regs.CMPA.bit.CMPA = INVThree_Output.fUpwmInv_A;
      EPwm1Regs.CMPB.bit.CMPB = INVThree_Output.fUpwmInv_A;

    We conducted a simulation experiment, when CMPA executed the assignment statement, and CMPB did not execute the load statement, there will be a short through phenomenon. In the follow picture, CH1 is ePWM1A, and CH2 is ePWM1B.

    2. ePWMxA and ePWMxB are configured as only one source. 

    That is, EPwm1Regs.DBCTL.bit.IN_MODE = 0x0; 

    We repeated many experiments, and there was no abnormal or short through phenomenon.

    Assignment statements for CMPA and CMPB are executed in the last part of CLA.The maximum interrupt execution time of CLA is only 52%. When the EPWM counter is 0 or 1500, the comparison value is loaded. We tested that the maximum EPWM counter is 1289, when the sampling and CLA are finished. 1289 is die not exceed 1500, CPMA and CPMB assignments should be completed before comparison value is loaded.

    We speculate that the long running time of CLA results in abnormal assignment of CPMA and CPMB. But we can not explain that the CLA running time did not exceed the interruption, Can you help us?.

    Thanks.

    Regards,

    Jetfan

  • Hi,

    I went through Configuration code and the results of the experiments you mentioned above.
    As such, the configuration seems alright to me. Using IN-MODE=2 in itself should not be causing any issue.
    If you are suspecting that the execution time of CLA is not enough - can you try below?
    Slow down the PWM ISR rate by half and check or take interrupts at half the rate. This should tell us if execution time indeed is the issue.
    I do not think CLA execution time is the issue though.
    Also, I see that the Sync (PHSEN) is enabled. Is there any sync signal coming in? Can you check if that is somehow effecting the counter status?
  • Hi,

    Were you able to resolve the issue. Please feel free to post an update if the issue persists.