CCS/TMS320F28379D: Unable to program CPU2

David Petryk

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE,

Tool/software: Code Composer Studio

I am getting the following error when trying to get a dual core application into the MCU.

Can anybody help me understand how to get this working. I did the blinky dual core example project and that went fine but I am unable to get my project to do the same thing.

The error indicates "No core matches the pattern 'CPU1'. Is there something that CPU1 must be running before CPU2 can be downloaded? I found another

post that asked the same question and I tried the suggested solution which worked for the original poster but it does not work in my case.

C28xx_CPU2: GEL Output:
Memory Map Initialization Complete
C28xx_CPU2: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. Also, CPU1 will be halted to determine SR ownership for the CPU which will run the Flash Plugin code, after which CPU1 will be set to run its application. User code execution from SR could commence after both flash banks are programmed.
C28xx_CPU2: Error occurred during flash operation: No core matches the pattern 'CPU1'
C28xx_CPU2: Error setting the GSxMSEL register for Flash operations
C28xx_CPU2: Error occurred during flash operation: Timed out waiting for target to halt while executing wr_pll.alg
C28xx_CPU2: Error writing the PLL values (Flash algorithm timed out). Operation cancelled.
C28xx_CPU2: Perform a debugger reset and execute the Boot-ROM code (click on the RESUME button in CCS debug window) before erasing/loading the Flash. If that does not help to perform a successful Flash erase/load, check the Reset cause (RESC) register, NMI shadow flag (NMISHDFLG) register and the Boot-ROM status register for further debug.
C28xx_CPU2: Error occurred during flash operation: No core matches the pattern 'CPU1'
C28xx_CPU2: File Loader: Memory write failed: Unknown error
C28xx_CPU2: GEL: File: C:\Users\Dave\workspace_v8\E8_Brain_CPU3\CPU2_FLASH_DEBUG\E8_Brain_CPU3.out: Load failed.
C28xx_CPU2: Error occurred during flash operation: No core matches the pattern 'CPU1'
C28xx_CPU2: Error setting the GSxMSEL register for Flash operations
C28xx_CPU2: Error occurred during flash operation: Timed out waiting for target to halt while executing pwrite_en.alg
C28xx_CPU2: Flash operation timed out waiting for the algorithm to complete. Operation cancelled.
C28xx_CPU2: Perform a debugger reset and execute the Boot-ROM code (click on the RESUME button in CCS debug window) before erasing/loading the Flash. If that does not help to perform a successful Flash erase/load, check the Reset cause (RESC) register, NMI shadow flag (NMISHDFLG) register and the Boot-ROM status register for further debug.
C28xx_CPU2: Error occurred during flash operation: No core matches the pattern 'CPU1'
C28xx_CPU2: Error occurred during flash operation: No core matches the pattern 'CPU1'
C28xx_CPU2: Error setting the GSxMSEL register for Flash operations

over 6 years ago

0 Vivek Singh over 6 years ago

TI__Guru** 113715 points

David,

Please confirm that you have CPU1 connected to CCS and halted while trying to program CPU2.

Also please check that you have installed latest CCS update. You can check for the same under "Help".

Regards,

Vivek Singh

0 Vamsi Gudivada over 6 years ago

TI__Guru* 87105 points

David,

I would like to take this opportunity to let you know that TMS320F2837x users should upgrade their CCS to 7.4 or greater. Please check below FAQ post for more details: e2e.ti.com/.../729543

If you already upgraded your CCS and updated the packages as listed in the above FAQ, you can ignore this.

In any CCS version, please note that CPU1 should be connected to debugger for CPU2 Flash Plugin operations to succeed.

Thanks and regards,
Vamsi

0 David Petryk over 6 years ago in reply to Vamsi Gudivada

Expert 1275 points

Vamsi,

I would like to elaborate a bit on where I think my problems are coming from. I have been in the business for a long time and I have much experience with MCU's and IDE's etc. I am having a hard time with CCS and the Delfino on several fronts. First its because I am new to both of these and there are a lot of secrets I have yet to discover. So let me paint a picture of where I am and hopefully that will help you help me more effectively.

I am having a hard time in two areas;

1. Getting a successful build of my code.
2. Downloading the code into the cpu.

After a some time working with CCS I can generate good code that the compiler is OK with. I have also examined many example programs to see how they are constructed. I have copied that same format and have noticed typically 3 ways to build the projects.

1. STANDALONE- FLASH
2. FLASH DEBUG
3. RAM DEBUG.

So I have a situation at the moment that I can build 2 out of 3. RAM DEBUG will not build saying there is not enough space. That is absurd because my code is tiny compared to that is available in the part. I am using a 28379D and there should be plenty of space. I get error messages saying that there are no "sections" and all sorts of other stuff that I dont really want to get into. I am used to just writing code at the C level and letting the compiler/linker/loader stuff it into the part. All of the compiler/linker/builder/debug scripts are Greek to me and I feel I should not have to customize them or know anything about them.

Is that a fair assumption?

Then when I try to debug the code it seems that a program written for CPU1 will not load into CPU2. So once again I start looking for some setting that I have set wrong or something? Not sure exactly what I am looking for. So I compare the myriad of settings for the project, linker, debug configurations to match the one for the example programs and I still cannot get it to work. So at the moment I have the project written for CPU1 being loaded into CPU1 & CPU2. Dont ask me how I did that but nothing I have done has been able to un-do it. It seems for example that there a re at least a half dozen places that have to be set to tell the environment that I want to use CPU2 or CPU1.

The basic problem is there seems many places that have to be exactly right for all of this to work. Is there a place to learn what all these settings do and how to set them correctly? Setting the debug configuration has places for settings I have no idea how or why it even needs this stuff.

So the first step is for you to help me understand what needs to be set and how for the various configurations the project has. And then there are all the aspects of running out of RAM vs. FLASH vs. DEBUG vs STANDALONE and so on.

Where to I go to get this information? Example projects are a great starting point but without understanding the fundamentals I will inevitably get stuck. AN I have not found any explanations.

I just want to load my code into FLASH, debug it and move on. Forget boot loaders for now. I just want to keep it simple for now so I can make some progress.

Please help me understand all the hidden secrets I need to know so I can make some progress. It should not be this hard.

Thanks, Dave.

0 David Petryk over 6 years ago in reply to David Petryk

Expert 1275 points

Here are some screen shots of the typical build errors..

0 David Petryk over 6 years ago in reply to David Petryk

Expert 1275 points

Another

0 David Petryk over 6 years ago in reply to David Petryk

Expert 1275 points

OK so I tried to upload the offending project into my cloud space CCS. I received the following error.

Just to be sure I am using the compiler version 18.9.0...

I dont understand why I would get this error.

Hopefully if I can load this into the cloud you will be able to get access to it ans help me solve some of the problems.

0 David Petryk over 6 years ago in reply to David Petryk

Expert 1275 points

I am unable to edit the properties using the cloud IDE unlike the local IDE. So I cannot change the compiler version

My suspicion is that the cloud IDE does not have the latest version of the C2000 compiler installed? What do you think?

Dave.

0 David Petryk over 6 years ago in reply to David Petryk

Expert 1275 points

So here is a contradiction (at least for me it is). This debug configuration for the dual core blinky application for "core selection" field shows that the load should be placed into CPU1. But in fact it loads into CPU2. So what is this setting actually doing? Its obvious to me that it is not doing the obvious.

0 Vivek Singh over 6 years ago in reply to David Petryk

TI__Guru** 113715 points

David,

Sorry to know that you are facing multiple issue on this. This started as code not loading on CPU2 but look like you are facing some basic issue with compile/linking itself. Linker cmd file is very unique to each project. Sample linker cmd file provided with example code may not work for every project and user need to update it as per their project requirement. You can find more detail on linker cmd file here.

The core selection in flash plug-in is done by tool itself based on which core you select. You don't have to change that. Also CPU1/CPU2 pre-defined in CCS properties is only for code compilation because there some resources on this device which are only accessible by CPU1 and not CPU2 but that should not prevent you from loading the code on CPU2. In the snapshot above, you have imported same project multiple time. You may want to clean that.

Along with example code in C2000Ware, you can refer this workshop which is specifically created for this device. Hope this helps.

Regards,

Vivek Singh

0 Ricky Lau over 6 years ago in reply to Vivek Singh

TI__Genius 12265 points

David,

I want to help look at the original issue you were seeing. You were getting the following issue:

"C28xx_CPU2: Error occurred during flash operation: No core matches the pattern 'CPU1'"

This error indicates that the flashing logic cannot find the CPU1 core in the configuration chain. Because CPU1 access is needed for CPU2 to gain access to the flash pump, it will fail to program the flash if CPU1 is not accessible. Can you attach the CCXML file you are using to configure for your device in CCS? I want to make sure the CPU1 core is configured correctly.

Thanks,
Ricky

0 David Petryk over 6 years ago in reply to Ricky Lau

Expert 1275 points

Hi Ricky,

Yes that is exactly the error I was getting. So I followed the exact procedure I used for the blinky DC project. I first connected to CPU1 and successfully downloaded CPU1 code. The debugger was stopped at main ready to go. Then I tried to load CPU2 code and ran into that error.

The ccxml file seems to be automatically created or possibly added to the project I'm not sure which.

I am unable to attach the file to this post cuz the system does not allow that extension od here is the file copied & pasted as text.

//=======================================================================

<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="configuration_0">
<instance XML_version="1.2" desc="Texas Instruments XDS100v2 USB Debug Probe" href="connections/TIXDS100v2_Connection.xml" id="Texas Instruments XDS100v2 USB Debug Probe" xml="TIXDS100v2_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS100v2 USB Debug Probe">
<instance XML_version="1.2" href="drivers/tixds100v2icepick_c.xml" id="drivers" xml="tixds100v2icepick_c.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds100v2c28x.xml" id="drivers" xml="tixds100v2c28x.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds100v2cla1.xml" id="drivers" xml="tixds100v2cla1.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds100v2cs_child.xml" id="drivers" xml="tixds100v2cs_child.xml" xmlpath="drivers"/>
<platform XML_version="1.2" id="platform_0">
<instance XML_version="1.2" desc="TMS320F28379D" href="devices/f28379d.xml" id="TMS320F28379D" xml="f28379d.xml" xmlpath="devices"/>
<device HW_revision="1" XML_version="1.2" description="" id="TMS320F28379D" partnum="TMS320F28379D" simulation="no">
<router HW_revision="1.0" XML_version="1.2" description="ICEPick_C router" id="IcePick_C_0" isa="ICEPICK_C">
<subpath id="Subpath_1">
<property Type="numericfield" Value="0x11" desc="Port Number_0" id="Port Number"/>
</subpath>
</router>
</device>
</platform>
</connection>
</configuration>
</configurations>

Thanks, Dave

0 David Petryk over 6 years ago in reply to Ricky Lau

Expert 1275 points

I have already posted a reply but now I don't see it.

Not sure where it went.

I'll get back to you guys.

0 David Petryk over 6 years ago in reply to David Petryk

Expert 1275 points

Now I see it. Sorry for the confusion.

0 David Petryk over 6 years ago in reply to Ricky Lau

Expert 1275 points

Ricky,

I am not sure whats going on but I responded to this thread the other day.

But when I looked I was missing my previous post. Then after posting my response again

I then saw the missing post. Now this time all of that is missing.

I am not sure if you are receiving my responses.

If you are please advise me that you are receiving them.

Thanks, Dave.

0 David Petryk over 6 years ago in reply to David Petryk

Expert 1275 points

OK its doing it again.

WTF?

0 David Petryk over 6 years ago in reply to David Petryk

Expert 1275 points

Have you had a chance to review the .ccxml file?

0 Ricky Lau over 6 years ago in reply to David Petryk

TI__Genius 12265 points

David,

Yes, I was able to see your previous posts.

It's a little difficult to see what is happening just based on the text you provided. So, can you run a few more tests for me?

1. Find the ccxml you are using and double click to open the Target Configuration view, and then go to the "Advanced" tab. I want to make sure you have the "C28xx_CPU1" core in your configuration. This is the string that the code is trying to match when looking for CPU1.

It should look something like this:

2. Right click on that ccxml and select "Launch Selected Configuration".

- After that, connect to both CPU1 and CPU2.

- When connected, go to 'Tools -> On-Chip Flash'. This should open the flash settings for your C28 cores.

- make sure CPU1 is selected, find the Erase button in the On-Chip Flash and click on it. See if this works.

- select CPU2, find the Erase button in the On-Chip Flash and click on it. See if this works.

Please let me know the test results for this.

Thanks,

Ricky

0 David Petryk over 6 years ago in reply to Ricky Lau

Expert 1275 points

Look at this;

https://youtu.be/bQoR7qCDjPg

0 Ricky Lau over 6 years ago in reply to David Petryk

TI__Genius 12265 points

David,

1. Is the screenshot not showing up for you? It was initially attached incorrectly, but I updated, and it seems to be showing up for me now.

But looking at your video, the "C28xx_CPU1" core seems to be available, so the ccxml looks ok.

2. Instead of "Launch Selected Configuration", can you choose "Debug As -> Code Composer Debug Session"? I think this should ask you which core you want to load your program to. Unselect all of the cores, and it should just launch the debug session. If you are able to get here, then follow the original steps again:

a) connect to both CPU1 and CPU2.
b) When connected, go to 'Tools -> On-Chip Flash'. This should open the flash settings for your C28 cores.
c) make sure CPU1 is selected, find the Erase button in the On-Chip Flash and click on it. See if this works.
d) select CPU2, find the Erase button in the On-Chip Flash and click on it. See if this works.

Thanks,
Ricky

0 Vivek Singh over 6 years ago in reply to Ricky Lau

TI__Guru** 113715 points

David, I hope reply from Ricky was helpful and you were able to resolve the issue.

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CCS/TMS320F28379D: Unable to program CPU2