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TMS320F28379D: Unable to configure HRCNFG register for ePWM in CPU2

Aditya Padmanabha
Expert 1440 points
Part Number: TMS320F28379D

Hi,

I am trying to run the example <C2000WAREINSTALLDIR>\device_support\f2837xd\examples\cpu1\hrpwm_deadband_sfo_v8 in CPU2. I am running GPIO initialization required for ePWM and allocating the ePWMs required to CPU2 in CPU1 as below

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
CpuSysRegs.PCLKCR2.bit.EPWM1 = 0;
CpuSysRegs.PCLKCR2.bit.EPWM2 = 0;
/* Assign used PWM modules to CPU2 */
DevCfgRegs.CPUSEL0.bit.EPWM1 = 1;
DevCfgRegs.CPUSEL0.bit.EPWM2 = 1;
EDIS;
InitEPwm1Gpio();
InitEPwm2Gpio();

Then I perform the rest of ePWM1 and ePWM2 configuration, setting up of ISR and modification of HR period, phase inside ISR in CPU2 after enabling the clock as below

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
EDIS;


//
// Init HRPWM1/HRPWM2
//
HRPWM1_Config(360);
HRPWM2_Config(360);

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Resync PWM timebase clock
(*ePWM[PWM1]).GLDCTL2.bit.OSHTLD = 1; // This should also write to
// GLDCTL2 of PWM2
EDIS;

//
// Configure ePWM1 to generate interrupts on period match
//
(*ePWM[PWM1]).ETSEL.bit.INTSEL = 1; // Interrupt on counter zero match
(*ePWM[PWM1]).ETSEL.bit.INTEN = 1; // Enable peripheral interrupt
(*ePWM[PWM1]).ETPS.bit.INTPRD = 1; // Generate interrupt on every event
PieCtrlRegs.PIEIER3.bit.INTx1 = 1; // Enable ePWM1 interrupt in PIE

IER |= 0x0004; // Enable core INT #3
EINT;

But when I check all the registers of ePWM1 and ePWM2 I see the values are set correctly except for HRCNFG register. I am not sure why this is happening. This issue is not present in CPU1 as I am able to run the example code properly in CPU1. And this issue affects only HRCNFG register and does not impact any other register settings.

I have attached screenshots from CCS with break point set to the particular instruction which will update HRCNFG register value for ePWM1, after executing the instruction by stepping over the code I still cannot observe the value in debug window but if I step through the next instruction which will set HRPE value in HRPCTL register it is updated properly.

I have also ensured that the ePWM1 and ePWM2 are allocated properly to CPU2 and clock is enabled for both ePWM1 and ePWM2.

I have also attached the source code which I have used for both CPU1 and CPU2.

CPU1

blinky_dc_hrpwm_init_cpu01.c
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//###########################################################################
//
// FILE: blinky_dc_hrpwm_init_cpu01.c
//
// TITLE: LED Blink Example along with required initialization for HRPWM to run in CPU2 for F2837xD.
//
//! \addtogroup dual_example_list
//! <h1> Blinky </h1>
//!
//! Dual Core Blinky Example. This example demonstrates how to implement
//! and run a standalone application on both cores.
//!
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.06.00.00 $
// $Release Date: Mon May 27 06:48:24 CDT 2019 $
// $Copyright:
// Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//
// Included Files
//
#include "F28x_Project.h"
#include "F2837xD_Ipc_drivers.h"
//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
InitSysCtrl();
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

CPU2

hrpwm_deadband_sfo_cpu02.c
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//###########################################################################
//
// FILE: hrpwm_deadband_sfo_cpu02.c
//
// TITLE: LED Blink and HRPWM with deadband Example for F2837xD.
//
// Dual Core Blinky Example. This example demonstrates how to run a
// implement a standalone application on both cores.
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.06.00.00 $
// $Release Date: Mon May 27 06:48:24 CDT 2019 $
// $Copyright:
// Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//
// Included Files
//
#include "F28x_Project.h"
#include "SFO_V8.h"
#ifdef _FLASH
//
// These are defined by the linker (see device linker command file)
//
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadSize;
extern Uint16 RamfuncsRunStart;
#endif
//
// Defines
//
#define PWM_CH 9 // # of PWM channels + 1
#define HR_ENABLED 1 // 1 = HR behavior
// 0 = non-HR behavior
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Please let me know how to solve this problem.

Thanks,

Aditya

  • 0
    TI__Guru 52010 points

    SFO is only available on CPU1 on this device.

  • 0 in reply to Nima Eskandari
    Expert 1440 points

    Hi Nima,

    Two questions

    1) Can you point me to the doc which says SFO is available only in CPU1? Does this mean we cannot consider MEP_ScaleFactor in any calculations for HRPWM in CPU2 or its just the SFO() function call will not work and this has to be done in CPU1?

    2) Also HRCNFG register is just not only about SFO right? for HRCNFG = 0x1353 we will have following values

    EDGEMODE = 3

    CTLMODE=0

    HRLOAD = 2

    SELOUTB = 0

    AUTOCONV = 1 (which will enable SFO)

    SWAPB = 0

    EDGEMODEB = 3

    CTLMODEB = 0

    HRLOADB = 1

    which will have impact on how the HRPWM waveform needs to respond right? But these values are not being set. In TRM only SyncSocRegs and EPwmXbarRegs are indicated to be available in CPU1. So then how to proceed with HRPWM configuration for this?

    Thanks,

    Aditya

  • 0 in reply to Aditya Padmanabha
    Expert 1440 points

    Hi Nima,

    Any updates on my queries?

    Thanks,

    Aditya

  • 0 in reply to Aditya Padmanabha
    TI__Guru 52010 points

    In this device, the HR configuration part of the ePWM modules only exists on ePWM1. Also SFO only runs on CPU1. Therefore ePWM1 must be allocated to CPU1 and SFO must run on CPU1.

  • 0 in reply to Nima Eskandari
    Expert 1440 points

    Hi Nima,

    Thanks, for the reply. 

    I am assuming this statement "In this device, the HR configuration part of the ePWM modules only exists on ePWM1." means that HRCNFG for ePWM works only for CPU1 and does not work on CPU2 for all ePWMs. Please correct me if I am wrong.

    Is this true for all multicore devices like F28388D for instance?

    Can you update the TRM for the devices with this additional information. I do not see this in our current version of TRM.

    Thanks,

    Aditya

  • 0 in reply to Aditya Padmanabha
    Expert 1440 points

    Hi Nima,

    Any updates on my previous queries?

    Thanks,

    Aditya

  • 0 in reply to Aditya Padmanabha
    TI__Guru 52010 points

    For F28388D device, eventhough CPU and EWPM1 still do the calibration for HRPWM, each EPWM module clocks the own HRPWM, and use the same copy of HRMSTEP calculated by the SFO. This allows HRPWM to function correctly with CPU2.

    Refer to the diagram in the TRM:

    HRPWM and HRCAL Source Clock