CCS/LAUNCHXL-F28069M: Unwanted phase-shift operation on a variable frequency and constant duty cycle resonant converter

asm(" EALLOW");
//    PCLKCR1.bit.EPWMxENCLK = 1: The ePWMx module is clocked by the system clock
SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1;
SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
asm(" EDIS");

EPwm4Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;    // Symmetric
EPwm4Regs.TBCTL.bit.PHSEN     = TB_DISABLE;         // Phase loading disabled
EPwm4Regs.TBCTL.bit.PRDLD     = TB_SHADOW;          // TBPRD register is loaded when TBCTR = 0
EPwm4Regs.TBCTL.bit.SYNCOSEL  = TB_SYNC_DISABLE;    // Disable PWM output synchronization signal
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;            // TBCLK = SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV    = TB_DIV1;            // TBCLK = SYSCLKOUT
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;         // CMPA register is not loaded until LOADAMODE event occurs
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;         // CMPB register is not loaded until LOADBMODE event occurs
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;       // load on CTR = Zero
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;       // load on CTR = Zero
EPwm4Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm4Regs.DBCTL.bit.IN_MODE  = DBA_ALL;                     // EPWMxA is the source for both falling-edge and rising-edge delay
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;              // Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
EPwm4Regs.DBCTL.bit.POLSEL   = DB_ACTV_HIC;                 // Active high complementary (AHC). EPWMxB is inverted
EPwm4Regs.DBFED = EPwm4Regs.DBRED = RESONANT_DBRED_DBFED;   // Load the dead band register
EPwm4Regs.ETPS.bit.INTPRD  = 1;          // Generate an EPWM4_INT interrupt every time one event occurs
EPwm4Regs.ETSEL.bit.INTSEL = 2;         // Enable event TBCTR = TBPRD
EPwm4Regs.TBPRD = RESONANT_MIN_TBPRD;
EPwm4Regs.CMPA.half.CMPA = RESONANT_MIN_TBPRD;
EPwm4Regs.TBPHS.half.TBPHS = 0x0000;                // Set timer phase
EPwm4Regs.TBCTR = 0;                                // clear TB counter

//    ePWM5:
EPwm5Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;    // Symmetric
EPwm5Regs.TBCTL.bit.PHSEN     = TB_DISABLE;         // Phase loading disabled
EPwm5Regs.TBCTL.bit.PRDLD     = TB_SHADOW;          // TBPRD register is loaded when TBCTR = 0
EPwm5Regs.TBCTL.bit.SYNCOSEL  = TB_SYNC_DISABLE;    // Disable PWM output synchronization signal
EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;            // TBCLK = SYSCLKOUT
EPwm5Regs.TBCTL.bit.CLKDIV    = TB_DIV1;            // TBCLK = SYSCLKOUT
EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;         // CMPA register is not loaded until LOADAMODE event occurs
EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;         // CMPB register is not loaded until LOADBMODE event occurs
EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;       // load on CTR = ZERO
EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;       // load on CTR = ZERO
//    EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR;                // Inverted in relation to EPwm4 - Full-bridge inverter implementation
//    EPwm5Regs.AQCTLA.bit.CAD = AQ_SET;
//    TODO Using same configuration as ePWM4 for the synchronization test
EPwm5Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm5Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm5Regs.DBCTL.bit.IN_MODE  = DBA_ALL;                     // EPWMxA is the source for both falling-edge and rising-edge delay
EPwm5Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;              // Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
EPwm5Regs.DBCTL.bit.POLSEL   = DB_ACTV_HIC;                 // Active high complementary (AHC). EPWMxB is inverted
EPwm5Regs.DBFED = EPwm5Regs.DBRED = RESONANT_DBRED_DBFED;   // Load the dead band register
EPwm5Regs.TBPRD = RESONANT_MIN_TBPRD;
EPwm5Regs.CMPA.half.CMPA = RESONANT_MIN_TBPRD;
EPwm5Regs.TBPHS.half.TBPHS = 0x0000;            // Set timer phase
EPwm5Regs.TBCTR = 0;                            // clear TB counter
asm(" EALLOW");                         // Enable EALLOW protected register access
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;  // Enable the clocks to the ePWM module after all ePWM modules are configured to ensure synchronization between the ePWM modules.
asm(" EDIS");                           // Disable EALLOW protected register access

__interrupt void INT13_ISR(void)     // INT13 or CPU-Timer1
{
	// Human-Machine-Interface code
	//...
	//...
}

__interrupt void EPWM4_INT_ISR(void)    // EPWM-4
{
	EPwm4Regs.ETCLR.bit.INT = 1;
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
	//...
	//(CONTROLLER ALGORITHM)
	//...
	EPwm4Regs.TBPRD = EPwm5Regs.TBPRD = new_period;           // PWM Period = ( 2 * TBPRD / F_SYSCLK ) for Up and Down Count mode ( Symmetric )
    EPwm4Regs.CMPA.half.CMPA = EPwm5Regs.CMPA.half.CMPA = EPwm4Regs.TBPRD >> 1;		// 50% duty cycle
}