TMS320F28377D: One question of ePWM phase delay.

Hi champs,

If we set below EPWM configurations for phase delay sync test,

1. EPWMCLKs of all EPWMs are 100MHz.
2. TBCLKs of EPWM1, EPWM2 and EPWM3 are 50MHz.
3. TBCLK of EPWM10 is 100MHz.
4. EPWM1 is sync master and will output sync pulse when TBCTR = 0.

Base on the settings above, we should get below EPWMs sync results, EPWM2, EPWM3 and EPWM10 will load TBCTR values from their TBPHS registers respectively when receiving the sync pulse from EPWM1, right?

According to Time-Base Counter Synchronization Scheme of TRM, there are internal delay, so the sync delay of EPWMs are not identical. My question is that what's the sync delay of EPWM2, EPWM3 and EPWM10 respectively when EPWM1 issues sync pulse?

Please advise your idea if any, thanks for help.

BR,

Luke