Does each of the LSx memory blocks has it's own arbitration logic?
Let's imagine the situation when CPU1 and CPU.CLA1 are running the code. CPU1 uses only LS1, CPU1.CLA1 uses only LS2.
What I'm interested in is whether CPU1 accesses to LS1 may delay CPU1.CLA1 accesses to LS2 (or vice versa) because of access arbitration ?
Is there a common arbitration logic for all LSx blocks or each of the LSx blocks has it's own arbitration ?
