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Tool/software: Code Composer Studio
Hello,everyone!
Now,I have a problem about software Phase Locked Loop and need your help.
In my code, "SPLL_1ph_SOGI_F.c" is used to lock grid phase. This file implements a software phase lock loop based on orthogonal signal generation using second order generalized integrators.
And, "SPLL_1ph_SOGI_F.c" is located in "controlSUITE\libs\app_libs\solar\v1.2".
I have done everything according to "controlSUITE\libs\app_libs\solar\v1.2\SolarLib.pdf\page86".
However, it doesn't work and I can't get the grid phase. WHY?
Q1:
In "controlSUITE\libs\app_libs\solar\v1.2\SolarLib.pdf\page86",
Step 4 – Using the module
spll1.u[0]=(Float32)(GridMeas);
what's the value of GridMeas? 220VAC/50Hz voltage is used in my program.
Q2:
Do I need to adjust these parameters?
// loop filter coefficients for 20kHz
spll_obj->lpf_coeff.B0_lf=(float32)(166.9743);
spll_obj->lpf_coeff.B1_lf=(float32)(-166.266);
spll_obj->lpf_coeff.A1_lf=(float32)(-1.0);
Thamks. I am looking forward to your reply.
1. Please note you are referring to controlSUITE code, these modules in controlSUITE are in non-maintained state. We have moved our collateral into C2000Ware-DigitalPower-SDK
2. The input for the module is vac measurement in per unit value which is +1 to -1
3. The coefficients for the loop filter need to be tuned, we provide an excel file to tune that, see spll_coeff_compute.xlsx
C:\ti\controlSUITE\libs\app_libs\solar\v1.2
4. We use this in several projects inside the C2000Ware-DigitalPower-SDK
see
TIDM-1007, TIDM-HV-1PH-DCAC code for the latest information and interface of the module, which brings this out more clearly.
The documentation is here:
file:///C:/ti/C2000Ware_DigitalPower_SDK_1_03_00_00/docs/html/dplib_html/group___s_p_l_l__1_p_h___s_o_g_i.html
You do not know the grid max value, but you know the sense circuitry you designed to sense that voltage (res dividers, op-amps etc). That will give you what will be the max that ADC can sense. Which is used for the per unit value calculation,