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TMS320F280049: how to understand the timing parameters for TMU

Aki Li
Genius 9365 points
Part Number: TMS320F280049

As indicated in table 2-1 in the TRM, operation a=b/c needs 5 pipeline cycles. Could you help explain how long it takes? I am not so clear about the relationship between pipeline cycle and CPU cycle. Thank you.

  • 0
    TI__Guru* 91125 points

    Aki,

    In the ideal case 1 pipeline cycle is equal to 1 CPU cycle.  The numbers given are for this ideal best case when nothing stalls the pipeline and the two values are equivalent.

    The cycles do not take into account something stalling the pipeline.  For example, a memory conflict, or memory wait states could stall the pipeline.  In this case 1 pipeline cycle would take multiple CPU cycles.   

    The number also do not include filling of the pipeline to start the code execution and assume the pipeline is already filled.  The cycle counts provided are effective cycles when executing code.  

    Regards

    Lori

  • 0 in reply to Lori Heustess
    TI__Genius 9365 points

    Lori,

    Thank you. For a=b/2pi, the pipeline cycles needed is 2/3, so it means 0.67 cycles or "2 or 3" cycles?

  • 0 in reply to Aki Li
    TI__Guru* 91125 points

    Aki Li said:
    For a=b/2pi, the pipeline cycles needed is 2/3, so it means 0.67 cycles or "2 or 3" cycles?

    Aki - it means 2 or 3.  Please refer to the description of the instruction itself. This can be found in the TMS320C28x Extended Instruction Sets TRM (http://www.ti.com/lit/spruhs1) for more details on the pipeline. 

    Regards

    Lori