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For Tyep 4 PWM in F28004x, if using Global Load feature, the shadow to active load event selection bits for individual shadowed registers are ignored and global load mode takes effect for the corresponding registers enabled by GLDCFG[REGx].
What if the new CMPA value to be updated at Global Load event when the new CMPA value is smaller than the present time-base counter value? If so, the compare event will be skipped, and the PWM output will be missed for one cycle?Is the above analysis correct? Is there suggestion to avoid this issue?
Hi,
Your understanding is correct. If the new compare value is smaller than the present time-base counter, the compare event is skipped.
I presume you are using s/w based global load hence you are concerned about the timing of the update.
You can still use global load and instead of s/w choose an event (cnt_zero, period match etc.) for reload.
In this case, the global load will occur on the next chosen event, and you'll not miss any compare events.