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TMS320F28027: Clarify ADC channel-to-channel errors

Wayne Huang
Genius 14385 points
Part Number: TMS320F28027

Dear Champs,

I am asking this for our customer.

In the user's application, they need to alternate the voltage and then get the corresponding current.

Now, they found an issue and we wonder if this is related to the ADC channel-to-channel errors.

Their setting is as follows:

SOC0    ADCINA4    ACQPS=8

SOC1    ADCINA3    ACQPS=8

SOC2    ADCINA6    ACQPS=8

SOC3    ADCINA7    ACQPS=8

All of the above use the same PWM triggering source with round robin setting.

ADCNONOVERLAP is set.

ADCCLK = 30 MHz

F28027 rev. A is used.

The user was trying to input alternating 0 and 3.3V in A6 and found that A7 reading was changing with the change of A6 from 0 to 3.3V and from 3.3V to 0. Note that the A7 channel was stable on the oscilloscope, but they output the A7 ADC readings to another PWM with Low-pass as DAC to observe it on the oscilloscope.

Note that in the testing, DC supply was used to input to A6 and A7 directly without any series resistors so that the ADC source impedance is very small.

By observation, 

This A7 reading changing with A6 input would become larger when A7 DC input is larger.

If both ACQPS of A6 (SOC2) and A7 (SOC3) were increased by a lot, then the A7 reading changing with A6 input would be no more.

If they did not alternate A6 input, then A7 reading would not be changing, either.

From the above, our questions:

Q1: Is this A7 reading changing with A6 input just the channel-to-channel gain variation (+-4LSB) and channel-to-channel offset variation (+-4LSB) documented in Talbe 6-26 (P76) of the datasheet (http://www.ti.com/lit/ds/symlink/tms320f28027.pdf)? Is this so-called cross-talk?

Q2: Why are there such channel-to-channel gain/offset variation?

Q3: After A6 is sampled by the internal sampling cap (Ch) and then changed to A7 by the multiplexer, the Ch will be charged from zero or from the last value of A6? We wonder if this explains why A6 affects A7 in this case?

Q4: To avoid such error, can they just change the SOC order so that A6 is in the last? like

SOC0    ADCINA4    ACQPS=8

SOC1    ADCINA3    ACQPS=8

SOC2    ADCINA7    ACQPS=8

SOC3    ADCINA6    ACQPS=8

Q5: With newer devices like F280049, which has up to 3x ADC modules and 3x S/H. If ADC A6 is allocated on ADC A, then all the ADC A signals measured after A6 will be affected, but other signals measured on ADC B and ADC C will not be affected. Is our understanding correct?

Wayne Huang

  • 0
    TI__Mastermind 22810 points

    Hi Wayne,

    Due to US Holidays please expect a reply by early next week.

    Best Regards,

    Marlyn

  • 0
    TI__Guru 62975 points

    Wayne Huang said:
    Q1: Is this A7 reading changing with A6 input just the channel-to-channel gain variation (+-4LSB) and channel-to-channel offset variation (+-4LSB) documented in Talbe 6-26 (P76) of the datasheet (http://www.ti.com/lit/ds/symlink/tms320f28027.pdf)? Is this so-called cross-talk?

    The channel-to-channel variation parameters are not related to the cross-talk as you have described. The datasheet variation parameters apply when the ADC is used under optimal conditions. It sounds like the ADC is not optimized in the experiment because the magnitude of the cross-talk decreases with increasing ACQPS selection.

    Wayne Huang said:
    Q2: Why are there such channel-to-channel gain/offset variation?

    Q3: After A6 is sampled by the internal sampling cap (Ch) and then changed to A7 by the multiplexer, the Ch will be charged from zero or from the last value of A6? We wonder if this explains why A6 affects A7 in this case?

    There is a note in the TRM for this:

    Wayne Huang said:
    Q4: To avoid such error, can they just change the SOC order so that A6 is in the last? like

    SOC0    ADCINA4    ACQPS=8

    SOC1    ADCINA3    ACQPS=8

    SOC2    ADCINA7    ACQPS=8

    SOC3    ADCINA6    ACQPS=8

    I would expect the error to transfer from A7 to A6.

    Wayne Huang said:
    Q5: With newer devices like F280049, which has up to 3x ADC modules and 3x S/H. If ADC A6 is allocated on ADC A, then all the ADC A signals measured after A6 will be affected, but other signals measured on ADC B and ADC C will not be affected. Is our understanding correct?

    Each ADC will still be susceptible to internal cross-talk between channels that share a single Ch capacitor. There should be negligible cross-talk between ADC modules.

    Cross-talk is generally mitigated through a combination of ACQPS selection and signal conditioning like adding capacitance to the ADC pin or using a high bandwidth buffer.

    I recommend reviewing the ACQPS guidelines in the F2806x TRM for reference -- these guidelines will be added to the F2802x TRM on the next refresh cycle.

  • 0 in reply to tlee
    TI__Genius 14385 points

    Dear tlee,

    Would you please clarify?

    1) In TI training for SAR ADC (in Chinese here), in min 23 sec 15, it says in the end of conversion, it will discharge Csh like below figure.

    So, this is different from the NOTE in the last post saying F2802x ADC does not have such Csh reset circuit (like S2).

    "That is no bias the Ch during conversions, no predetermined ADC conversion value like zero. "

    Is our understanding right?

    If yes, is there any concern that F2802x does not have such discharge reset circuit here?

    2. As there is residue charge on the Ch, is it possible that there is negative current from the ADC pin to the external circuits if the next ADC sample voltage is lower than Ch residue voltage?

    Wayne Huang

  • 0 in reply to Wayne Huang
    TI__Guru 62975 points

    Wayne Huang said:
    1) In TI training for SAR ADC (in Chinese here), in min 23 sec 15, it says in the end of conversion, it will discharge Csh like below figure.

    So, this is different from the NOTE in the last post saying F2802x ADC does not have such Csh reset circuit (like S2).

    "That is no bias the Ch during conversions, no predetermined ADC conversion value like zero. "

    Is our understanding right?

    If yes, is there any concern that F2802x does not have such discharge reset circuit here?

    Right, there are many different ADC architecture variants. There is no Ch discharge switch on F2802x. There is no absolute right or wrong way to implement the preconditioning of the Ch capacitor.

    The cross-talk can be mitigated with signal conditioning and ACQPS selection.

    Wayne Huang said:
    2. As there is residue charge on the Ch, is it possible that there is negative current from the ADC pin to the external circuits if the next ADC sample voltage is lower than Ch residue voltage?

    Yes, this can happen. It is possible to model the behavior using the component values from the ADC input model.