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TMS320F28069: I2C Module FIFO Transmit Interrupt

Jawwad Hafeez
Intellectual 870 points
Part Number: TMS320F28069

Hi, 

I am using i2c module on 320F28069. I am using FIFO.

I2caRegs.I2CCNT =WrSize;
I2caRegs.I2CSAR =SlaveAddress;
I2caRegs.I2CFFTX.bit.TXFFIL = 0;

When I write 4 bytes, i get fifo tx interrupt after 2 bytes and interrupt is generated.

No further bytes are sent. No interrupt generated. Any pointers or directions, what to look for.

Regards

Jawwad

  • 0
    TI__Mastermind 42976 points

    Hi Jawwad,

    The interrupt you say is being generated is the I2CFFTX.TXFFINT interrupt, correct? What is your I2CFFTX.TXFFIL register set to if so?

    Best,

    Kevin

  • 0 in reply to Kevin Allen18
    Intellectual 870 points

    Thank Kevin for the reply.

    Yes I am using  I2CFFTX.TXFFINT and  I2CFFTX.RXFFINT. XRDY and RRDY Interrupts are disabled, and I2caRegs.I2CFFTX.bit.TXFFIL = 0;

    i think I have some error on bus that I am not addressing properly. I think I am not properly addressing the NACK received during the communication. 

    What is ur opinion. Should i enable NACKint and send a stop after receiving that NACK. Or should I just check NACKint in a FIFO Interrupt and send stop if received. By the way the interrupt is programmed to occur for : TXFFINT, RXFFINT, ARDYINT,SCDINT . 

    Regards

  • 0 in reply to Jawwad Hafeez
    TI__Mastermind 42976 points

    Hi Jawwad,

    Jawwad Hafeez said:
    What is ur opinion. Should i enable NACKint and send a stop after receiving that NACK.

    I think this is the correct way. Here's how I handled it in the past, however this isn't interrupt based:

                if(I2caRegs.I2CSTR.bit.NACK == 1)
            {
                I2caRegs.I2CMDR.bit.STP = 1;
                I2caRegs.I2CSTR.all = I2C_CLR_NACK_BIT;

                Status = I2C_ERROR;
                return Status;
            }

    If you're able to probe the bus, ideally with a logic analyzer, that should help you in your debug.

    Best,

    Kevin

  • 0 in reply to Kevin Allen18
    Intellectual 870 points

    Hi Kevin.

    Thanks for the help. I resolved the problem. Took some experimentation to understand the concept of working of TIs i2c. The base problem was that the FIFO with 4 bytes would send only 2 bytes and would stop sending any further data, no matter u write I2caRegs.I2CMDR.all = 0x6E20; //Transmit FIFO, again and again.
    The receiver in my case was sending a NACK after 2 bytes and i was not handling NACK properly. That halted any future transmissions. I had to do reset FIFO by doing:

    I2caRegs.I2CFFTX.bit.TXFFRST=0;
    usec(10); //Dumy delay 
    I2caRegs.I2CFFTX.bit.TXFFRST=1;

    this resolved the issue.

    Next i will check what dummy delay is required to ensure that FIFO is reset and enabled. Currently 10usec is a dummy delay, some empty counting instructions to ensure bit is cleared

    The relevant code is as follows. I would also request TI to comment plz, if this is the best solution, any other leads appreciated. I use TIRTOS 

    //Enabled I2c Interrupt as follows
    I2caRegs.I2CIER.all = 0x24; // Enable SCD & ARDY interrupts
    I2caRegs.I2CFFTX.all = 0x6020; // Enable FIFO mode and TXFIFO
    I2caRegs.I2CFFRX.all = 0x2040; // Enable RXFIFO
    I2caRegs.I2CFFTX.bit.TXFFINTCLR = 1; //Clear TXFFINT
    I2caRegs.I2CFFRX.bit.RXFFINTCLR = 1; //Clear RXFFINT

    //In interrupt routine, if ARDY int check for NACK 
    if(IntSource == I2C_ARDY_ISRC){
    if(I2caRegs.I2CSTR.bit.NACK == 1){
    I2caRegs.I2CMDR.bit.STP = 1; //if NACK send stop
    I2caRegs.I2CSTR.all = I2C_CLR_NACK_BIT; //Clear NACK 
    I2C.ErrCode = I2C_NACK_ERROR; //Set error code for checking
    I2C.WrDone=0; //Flag i2c write that writing done 
    }
    }
    //In I2C Write function 
    msg->WrDone=1;
    I2caRegs.I2CMDR.all = 0x6E20; //Transmit FIFO
    while(msg->WrDone); //Wait for WrDone, cleared by i2c interrupt routine, this is test code, 
    //don't use blocking wait in production software, better use for with dealy or a supervisor
    if(msg->ErrCode==I2C_NACK_ERROR){
    I2caRegs.I2CFFTX.bit.TXFFRST=0;
    usec(10);
    I2caRegs.I2CFFTX.bit.TXFFRST=1;
    return -1;
    }