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CCS/TMS320F28069: ePWM Dead Band

ruediger.gerfried
Intellectual 880 points
Part Number: TMS320F28069

Tool/software: Code Composer Studio

Hello Hotline,

I  initialed the TBCTL Register with CLKDIV 0 and HSPCLKDIV 0 -> the timebase was clocked with SYSCLK (e.g. 80MHz) and then the DB Generator adjusted using Half Clock Cycle -> 2* SYSCLK?. How can that happen.

Best Regards

Gerfried

  • 0
    TI__Mastermind 42195 points

    Gerfried,

    to make sure I understand what you are saying please confirm my statements.

    1. You set TBCTL.CLKDIV = 0
    2. You set TBCLK.HSPCLKDIV = 0
    3. You then set PCLKCR1.EPWMxENCLK = 1
    4. Finally you see DBCTL.HALFCYCLE become equal to 1, but you did not mean to write this bit, correct?

    Please make sure you have enabled the module clock before you set your peripheral configuration. Secondly have you tried adding breakpoints in your code to determine exactly when the DBCTL.HALFCYCLE bit is being set? That bit is not set automatically by hardware, so something in your code likely did this.

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Intellectual 880 points

    Hello Cody,

    thank you for your quick answer.

    Init: first 3. (PCLKCR1.EPWMxENCLK = 1) and then 1,2,4...

    but I only not understand why db generator works with 2*SYSCLKOUT, when the highest

    frequenzy for ePWM is SYSCLKOUT.

    Are there a document with full explanation?

    Regards

    Gerfried

  • 0 in reply to ruediger.gerfried
    TI__Mastermind 42195 points

    Gerfried,

    The Technical Reference Manual explains everything you need to know to use this feature. In this case I do not think we provide exactly how half-cycle clocking is implemented.

    Please following the instructions in the TRM, its should be pretty simple, just enable it and be sure to adjust your Dead-Band delay values according to the new formula.


    Regards,
    Cody