CCS/TMS320F280049C: TMS320F280049 Phase shift full bridge PCMC issue

Hello i'm gibum Yu 

i'm study about peak current mode of Phase-shift full bridge converter with 28004x launch pad.

I set my register like datasheet 

it works well but some point is not worked 

1. Slow slope and low Vdac

2. Fast slope and high Vdac

there is my code

Cmpss1Regs.COMPCTL.bit.COMPDACE = 1; // 1 : Enable CMPSS

Cmpss1Regs.COMPDACCTL.bit.DACSOURCE = 1; // 1 : DACHVALA is updated from the ramp generator

Cmpss1Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC; //NEG signal comes from DAC
Cmpss1Regs.COMPCTL.bit.COMPHINV = 0; // 0 : Output of comparator is not inverted 1 : Output is inverted

Cmpss1Regs.COMPCTL.bit.ASYNCHEN = 1; // 1 : Enable high comparator asynchronous path (Digital filter is not used)

Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH; // Configure CTRIPOUT path (Go to EPWM X-BAR)
Cmpss1Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA; // DAC - p1691
Cmpss1Regs.COMPDACCTL.bit.RAMPLOADSEL = 1; // Ramp generator - p1693
Cmpss1Regs.COMPDACCTL.bit.RAMPSOURCE = 4; // Ramp generator source select. 4 : EPWM5SYNCPER (kb)

Cmpss1Regs.RAMPDLYS.bit.DELAY = 0; // initial
Cmpss1Regs.RAMPDECVALS = 0; // initial
Cmpss1Regs.RAMPMAXREFS = 65535; // initial

// CMP"H" configuration End //

// CMP"L" configuration //
// CMPSS module - p1690
Cmpss1Regs.COMPDACCTL.bit.SWLOADSEL = 1; // 1 : DACxVALA is updated from DACxVALS on EPWMSYNCPER
Cmpss1Regs.COMPCTL.bit.COMPLSOURCE = 0; // 0 : Inverting input of comparator driven by internal DAC
Cmpss1Regs.COMPCTL.bit.COMPLINV = 0; // 0 : Output of comparator is not inverted 1 : Output is inverted
Cmpss1Regs.COMPCTL.bit.CTRIPLSEL = 2; // 2 : Output of digital filter drives CTRIPL (Go to EPWM X-BAR)
// CMP"L" configuration End //

// Digital filter configuration //
// CTRIPLFILCTL CTRIPHFILCLKCTL
Cmpss1Regs.CTRIPLFILCTL.bit.FILINIT = 1; // Initialize all samples to the filter input value
Cmpss1Regs.CTRIPLFILCTL.bit.SAMPWIN = 7; // Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
Cmpss1Regs.CTRIPLFILCTL.bit.THRESH = 5; // Threshold used is THRESH+1
Cmpss1Regs.CTRIPLFILCLKCTL.bit.CLKPRESCALE = 0; // Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1.
// Digital filter configuration End //

// EPWM X-BAR Configuration //
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX1 = 0; // CMPSS1.CTRIPH for OCP -> TRIP4
EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX0 = 0; // CMPSS1.CTRIPL for PCMC -> TRIP5

EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX1 = 1; // Enable
EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX0 = 1; // Enable

EPwmXbarRegs.TRIPOUTINV.bit.TRIP4 = 0; // Active High
EPwmXbarRegs.TRIPOUTINV.bit.TRIP5 = 0; // Active High

//Cycle by cycle TZCTL2 setting
EPwm2Regs.TZCTL2.bit.ETZE = 1; // TZCTL2 Enable
EPwm2Regs.TZCTL2.bit.TZAU = 7; // 7 : Do Nothing, trip action is disabled;
EPwm2Regs.TZCTL2.bit.TZAD = 2; // 2 : Forced Lo
EPwm2Regs.TZCTL2.bit.TZBU = 2; // 2 : Forced Lo
EPwm2Regs.TZCTL2.bit.TZBD = 7; // 7 : Do Nothing, trip action is disabled;

//Initialize TZFLG
EPwm2Regs.TZFLG.bit.DCAEVT1=0;
EPwm2Regs.TZFLG.bit.DCAEVT2=0;
EPwm2Regs.TZCLR.bit.DCAEVT1=1;
EPwm2Regs.TZCLR.bit.DCAEVT2=1;

EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TRIPIN5; // 0x4 : TRIPIN5 DCAH==TRIP5
EPwm2Regs.DCTRIPSEL.bit.DCALCOMPSEL = DC_TRIPIN4; // 0x3 : TRIPIN4 DCAL==TRIP4

EPwm2Regs.TZDCSEL.bit.DCAEVT2 = 2; // For PCMC - CBC trip p1875
// 010 : DCAH = high, DCAL = dont care
EPwm2Regs.TZDCSEL.bit.DCAEVT1 = 4; // For Protection - OSHT trip
// 100 : DCAL = high, DCAL = dont care

// DCAEVT2 Configuration for PCMC // p1878
EPwm2Regs.DCFCTL.bit.SRCSEL = DC_SRC_DCAEVT2; // 01 : Source is DCAEVT2 signal
EPwm2Regs.DCFCTL.bit.BLANKE = DC_BLANK_ENABLE; // 1 : Blanking window is enabled
EPwm2Regs.DCFCTL.bit.PULSESEL = 2; // 00 : TBCTR=TBPRD 01 : TBCTR=ZERO 10 : TBCTR=TBPRD or TBCTR = ZERO 11 : X
EPwm2Regs.DCFOFFSET = 193; // Offset value
EPwm2Regs.DCFWINDOW = 10; // Window value
EPwm2Regs.DCFCTL.bit.BLANKINV = 0; // Not invert

EPwm2Regs.DCACTL.bit.EVT2SRCSEL = 1; // DCAEVT2 Event triggering. p1876

// DCEVTFILT Source Signal Select. 0: Source Is DCAEVT1 Signal
EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0; // 0 : Async path -> generate DCAEVT1.force

// 이미 DCAEVT1.force로 연결해 놨는데 DCEVTFILT를 트리거로 ?
EPwm2Regs.AQTSRCSEL.bit.T1SEL = 8; // 0x1000 : DCEVTFILT 0x0000 : DCAEVT2 p1865 p1950
EPwm2Regs.TZSEL.bit.DCAEVT2 = 1; // Enable DCBEVT2 as a CBC trip source for this ePWM module CBC trip enable

// DCAEVT1 Configuration for Protection //
EPwm2Regs.DCACTL.bit.EVT1SRCSEL = 0; 
EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = 1; // 1 : Async path -> generate DCAEVT1.force
EPwm2Regs.TZSEL.bit.DCAEVT1 = 1; // 1 : Enable DCBEVT1 as one-shot-trip source
EPwm2Regs.TZEINT.bit.DCAEVT1 = 1; // 1 : Digital Compare Output A Event 1 Interrupt Enable

EPwm2Regs.TZCLR.bit.CBCPULSE = 2;