TMS320F28035: IEC60730 test for ST1 and RPC

Terry Deng

Part Number: TMS320F28035

Dears

Customer is developing their project base on F28035 and take C2000MCU_IEC60730_4_00_01_00 as reference, the reference firmware has include ST0 test case, however do not include the test item for ST1 and RPC register, which the IEC certification company require they must do.

So customer add the test item for ST1 and RPC register according the same method which TI reference firmware for ST0 test. However the CPU will stop running after add the ST1 and RPC test case. Could you please help check customer code as below if it is right? If no, could you help suggest the correct method to test ST1 and RPC register?

/***************Below is TI reference firmware for ST0 test********************************/

PUSH ST0
POP @PL ; save ST0 in PL
PUSH @AL
POP ST0 ; write to ST0
PUSH ST0
POP AR4
CMP AL,@AR4
B fail_CPU_test,NEQ
PUSH @PL
POP ST0 ; restore ST0

/***************Below is customer firmware for ST1 and RPC test********************************/

PUSH ST1
POP @PL ; save ST1 in PL
PUSH @AL
POP ST1 ; write to ST1
PUSH ST1
POP AR4
CMP AL,@AR4
B fail_CPU_test,NEQ
PUSH @PL
POP ST1 ; restore ST1

PUSH RPC
POP @PL ; save RPCin PL
PUSH @AL
POP RPC; write to RPC
PUSH RPC
POP AR4
CMP AL,@AR4
B fail_CPU_test,NEQ
PUSH @PL
POP RPC; restore RPC

over 5 years ago

0 Terry Deng over 5 years ago

TI__Expert 3005 points

we continue debug and found the JTAG connection will broken if write ST1 register，or can not return from the function if write RPC register。

Who can help advice how to handle ST1 and RPC in IEC60730 certification？

0 Ashish Vanjari over 5 years ago in reply to Terry Deng

TI__Intellectual 1110 points

Hi Terry,

Both RPC and ST1 reqgiter can affect CPU operations. I will work on exploring correct sequence and get back to you in few days.

Regards,

--Ashish

0 Whitney Dewey over 5 years ago in reply to Terry Deng

TI__Guru 54185 points

Hi Terry,

Try this code for the RPC. It may need some optimization, but it worked well when I tested it. I put it in the code right after the SP test.

    ;
    ; Test return program counter
    ;
rpcRegTest:
        MOVL    XAR6, @ACC              ; save ACC contents

        AND     AH, #RPC_TEST_MASK_MSB ; RPC is 22 bits

        PUSH    RPC
        POP     P                       ; save RPC in P

        PUSH    ACC
        POP     RPC                     ; write to RPC
        PUSH    RPC
        POP     XAR4
        CMPL    ACC, XAR4
        B       failRPCTest, NEQ

        NOT     ACC
        AND     AH, #RPC_TEST_MASK_MSB
        PUSH    ACC
        POP     RPC                     ; write to RPC
        PUSH    RPC
        POP     XAR4
        CMPL    ACC, XAR4
        B       failRPCTest, NEQ
        B       restoreRPC, UNC

failRPCTest:
        PUSH    P
        POP     RPC                     ; restore RPC
        B       fail_CPU_test, UNC

restoreRPC:
        PUSH    P
        POP     RPC                     ; restore RPC
        MOVL    ACC, @XAR6              ; restore ACC contents

I need to look into ST0 a bit more.

Edit: Should have mentioned RPC_TEST_MASK_MSB should be defined as 0x003F.

Whitney

0 Whitney Dewey over 5 years ago in reply to Whitney Dewey

TI__Guru 54185 points

Okay, for ST1, I expect that all the backward compatibility modes are set to C28x mode and can be assumed constant values. For the R/W fields, you can use something like the following.

ST1_CLR_TEST_MASK .set 0xFF5B
ST1_SET_TEST_MASK .set 0x0A00

st1RegTest:
        MOVL    XAR6, @ACC              ; save ACC contents
        AND     IER, #0                 ; clear IER so we can test INTM

        AND     AL, #ST1_CLR_TEST_MASK ; clear the bits that need to stay 0
        OR      AL, #ST1_SET_TEST_MASK ; set the bits that need to stay 1

        PUSH    @AL
        POP     ST1                     ; write to ST1
        PUSH    ST1
        POP     AR4
        CMP     AL, @AR4
        B       fail_CPU_test, NEQ

        NOT     ACC
        AND     AL, #ST1_CLR_TEST_MASK ; clear the bits that need to stay 0
        OR      AL, #ST1_SET_TEST_MASK ; set the bits that need to stay 1

        PUSH    @AL
        POP     ST1                     ; write to ST1
        PUSH    ST1
        POP     AR4
        CMP     AL, @AR4
        B       fail_CPU_test, NEQ

        MOVL    ACC, @XAR6              ; restore ACC contents

I placed the code after the loop_REG_2_test loop but before the 16-bit registers are restored. You'll also need to add ST1 to the saves and restores that happen in that section--save it to one of the ARn registers that isn't already being used for something else.

Note that the code above doesn't take care of the read-only bits IDLESTAT and LOOP. If a low power mode is being used, IDLESTAT can be indirectly tested by doing a functional test of the low power mode. LOOP can be tested by executing the LOOPZ or LOOPNZ and using an interrupt or timer to break the loop. If you use an interrupt, you may even be able to read ST1 off the stack and confirm that LOOP was set to 1.

Whitney

0 Ashish Vanjari over 5 years ago in reply to Whitney Dewey

TI__Intellectual 1110 points

Hi Terry,

Hope this resolved your query. Feel free to send us a question if not resolved.

Regards,

--Ashish

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TMS320F28035: IEC60730 test for ST1 and RPC