This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280049C: How long is the latch time of CMPSS SR latch module

Part Number: TMS320F280049C

Hi Expert,

There's a situation that customer need to clear the COMPHLATCH bit, once the bit is "set", however, they find that sometimes the "bit" could not be cleared by the first time, so they wonder if this is because the "1" is still latched at the first clearing time.

Have you met this condition, and what do you think about it? Thanks!

Best Regards

Rayna

  • Hi Rayna,

    It's possible that when the latch is cleared, the comparator output is still high so it immediately sets the latch after the clear. They need to make sure the comparator is not high before the latch is cleared if having the latch stay cleared is important in their use-case.

  • Hi Frank,

    Thanks for your reply.I'll let customer check what you said.

    One more question, if comparator is not high before the latch is cleared, whenever the COMPHLATCH could be cleared, even if when clear action and comparator output dropping to low occurs at the same time, is that right?

    Thanks!

    Best Regards 

    Rayna

  • Rayna,

    The snapshot below from the TRM might help explain it. Also, keep in mind LATCHCLR is EALLOW protected. Let us know if it's still not clear.