TMS320F28377D: Capacitance of GPIO can be paralled

Jason Whiles do we have a number defined for this? Or do we just ask the user to understand the RC circuit and the current/time it will take to charge the cap. if the Cap is too large we are basically short circuiting the GPIO for a time-constant duration?

Cheney_Sun,

Could you provide more details on what you are trying to achieve with this implementation?  That would help us to provide the best direction.

It is not typical to add intentional capacitance to a signal line; but initial motivations would typically be noise-filtering, introducing delay, or slowing down edge rates.  However this will increase power consumption and could create other issues.  

In most cases a capacitor by itself could make noise susceptibility worse since it increases the time a signal spends in the mid-voltage region which can be interpreted as glitches to the receiving IC.  PCB trace spacing and good signal integrity practices are a better solution if this is a noise-victim concern.

If the intent is to slow the edge rate to keep this from being an aggressor, then a series resistor close to the F28377 device will be more effective when combined with the parasitic capacitance of the trace.

If the intent is RC delay then you would also want a series resistor between the capacitor and the external capacitance.

To answer your direct question, a large external capacitance could create power supply noise or reliability issues on the F28377 device because it presents a short circuit to VSS during switching.  The absolute maximum of 20mA output current should always be observed, and if repeated I would recommend limiting current to 2mA.  A series resistor can be used to address this as well, depending on your edge-rate needs and the capacitance of the rest of the circuit then anywhere from 20Ohm to 500Ohm may be sufficient.  You should calculate the RC time constant you need.

Hope this helps.

Best regards,

Jason