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I2C FIFO interrupt

Kerson B.
Prodigy 120 points

I can't seem to clear the FIFO interrupt flag on the F28035 DSP. I tried clearing the interrupt using the TXFFINTCLR bit on the F2808 DSP and it works fine.

On the F28035, the interrupt flag goes high as soon as the FIFO transmitter is enabled and only goes low when the FIFO transmitter is disabled. TXFFIL doesn't affect this interrupt either.

The RXFFINT works just fine, btw. RXFFINTCLR clears it as it should. Does the TXFFINT operate differently than the RXFFINT? or is there something else I'm missing?

 

Regards,

Kerson.

 

  • 0
    Prodigy 140 points

    Hi,

    Correction: The TX FIFO interrupt triggers on less than or equal to the TXFFIL level. So do not enable the interrupt unless you have loaded values (i.e. at the start of transmission). Then, when the data is sent, the FIFO level drops, and an interrupt occurs to let you know to either add more data to the FIFO, or disable the interrupt if you are done.

    The following applies to the Rx FIFO with a greater than or equal to trigger level:

    Have you set the TXFFIL4-0 bits to something > 0? If the interrupt is set to trigger at a FIFO level of 0, then the interrupt will assert and reassert continuously.

     

    Nate

  • 0 in reply to Nathan Goslee
    Prodigy 120 points

    Hey Nate,

    Looks like there was a slight misunderstanding with my earlier post. What I wanted to say was:

    1. The interrupt works just fine for the receiver (RXFF).

    2. The interrupt works just fine for the transmitter (TXFF) and receiver (RXFF) on the F2808 DSP.

    3. The interrupt goes high regardless of TXFFIL's value on the F28035.

    The same method I used to configure the receiver (RXFF) interrupt is the same one I used for the transmitter on both the F28035 and the F2808. It works just fine except for the TXFFINT on the F28053 and that flag doesn't clear regardless of what I have tried so far. I can't figure what I'm missing.

    Here's the last attempt I made at clearing that interrupt on the F8035:

        I2caRegs.I2CFFTX.all = 0x6044;    // Enable FIFO mode and TXFIFO;
        EALLOW;
        I2caRegs.I2CFFTX.bit.TXFFINTCLR = 1;
        EDIS;
        I2caRegs.I2CFFRX.all = 0x2044;    // Enable RXFIFO, clear RXFFINT;

    The FFRX one works just fine, as I've said before. I am not using any of the FIFO interrupt so I stopped worrying about this a while ago. If you can actually clear that bit, do let me know.

    Regards,

    Kerson.

     

  • 0 in reply to Kerson B.
    Prodigy 140 points

    Hi Kerson,

    I'm not familiar with the F2808, but on the F28035, any value of TXFFIL will cause the interrupt to set if  the FIFO is empty. I ran into this with the SCI port. When I have data to transmit, I enable the interrupt. Then the Tx FIFO interrupt triggers and the isr loads the data. When the queue is empty, the isr disables the interrupt.

    Hope that was somewhat clear, only enable the interrupt if you are actively transmitting, otherwise (as you noted) it will continually assert itself.

    Nate