CCS/TMS320F28379D: Phase-shift PWM

Takayuki Miyazaki

Part Number: TMS320F28379D
Other Parts Discussed in Thread: TMS320F28388D, C2000WARE

Tool/software: Code Composer Studio

Hi Experts

Our customer is developing their system with F28388D. Although customer is evaluating PWM signals, customer observed strange waveform. I attached this one(TMS320F28388D_PWM_Issue_2020_1026.pdf). Operating frequency is 100kHz. Customer is using driverlib on C2000Ware during PWM configuration. Customer was looking into this issue on E2E and notice the similar issue was reported as following thread, however, they cannot find any solution on this thread.

https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/376207?F28069-ePWM-phase-shift-problem

I attached customer's source code(

Fullscreen 20201026_drv_epwm_c2.c Download

/*
 * drv_epwm.c
 *
 *  Created on: 2019/09/12
 */
#include "F28x_Project.h"
#include <SFO_V8.h>

#include <stdint.h>
#include <stdbool.h>

#include <sysctl.h>
#include <epwm.h>
#include <inc/hw_epwm.h>
#include <inc/hw_memmap.h>
#include <driver/drv_epwm_c2.h>
#include <driver/drv_hrpwm_c2.h>

void InitEPwm1(void);
void InitEPwm2(void);
void InitEPwm3(void);
void InitEPwm4(void);
void InitEPwm5(void);
void InitEPwm6(void);
void InitEPwm12(void);   //For measurement 0f CLA internal calculation performance

//======================================
//For High resolution PWM calibration
//======================================
int MEP_ScaleFactor; //Global variable used by the SFO library
                     //Result can be used for all HRPWM channels
                     //This variable is also copied to HRMSTEP
                     //register by SFO(0) function.

// Used by SFO library (ePWM[0] is a dummy value that isn't used)
volatile uint32_t ePWM[PWM_CH_MAX + 1] = {0, EPWM1_BASE, EPWM2_BASE, EPWM3_BASE, EPWM4_BASE};

//*****************************************************************************
// EPWM�̏�����
// ���� �Ȃ�
// �߂�l �Ȃ�
//*****************************************************************************
void init_EPwm(void){
    InitEPwm1();    //PWM for high-voltage class D amplifier
    InitEPwm2();    //PWM for high-voltage class D amplifier
    InitEPwm3();    //PWM for high voltage DCDC converter
    InitEPwm4();    //PWM for high voltage DCDC converter
    InitEPwm12();   //For measurement 0f CLA internal calculation performance
    SFO();
}

//*****************************************************************************
// ������\PWM�̃L�����u���[�V����
// ��莞�ԊԊu�ŕK�����s����B
// ���� �Ȃ�
// �߂�l �Ȃ�
//*****************************************************************************
void HrPwmCal(void){
    SFO();//PWM Calibration
}

//*****************************************************************************
// EPWM1�̏�����
// ����D���A���v�pPWM�o�� �p���X����
// ���� �Ȃ�
// �߂�l �Ȃ�
//*****************************************************************************
void InitEPwm1(void){
    EALLOW;

    //Stop PWM Timer PWM���W�X�^�ݒ莞�N���b�N������K����~����
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    //--------------------------------------------------------------------
    //Time-Base(TB) Module configuration
    //--------------------------------------------------------------------
    //�ݒ�l�l�𑦔��f����
    EPWM_setPeriodLoadMode(EPWM1_BASE, EPWM_PERIOD_DIRECT_LOAD);
    //�^�C�}�J�E���g�A�b�v
    EPWM_setTimeBaseCounterMode(EPWM1_BASE, EPWM_COUNTER_MODE_UP);
    //PWM�����̐ݒ�
    EPWM_setTimeBasePeriod(EPWM1_BASE, EPWM1_PERIOD - 1);
    //�ʑ��V�t�g���[�h���Ȃ� EPWM��œ��삳���邽��
    EPWM_disablePhaseShiftLoad(EPWM1_BASE);
    //�ʑ��̐ݒ� Master��0��
    EPWM_setPhaseShift(EPWM1_BASE, 0);
    //�J�E���^�l�̃N���A
    EPWM_setTimeBaseCounter(EPWM1_BASE, 0);
    //�����M����o�͂���
    EPWM_enableSyncOutPulseSource(EPWM1_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);    //Counter zero event generates EPWM sync-out pulse

    //--------------------------------------------------------------------
    //Configuration for PWM Clock Division 
    //--------------------------------------------------------------------
    EPWM_setClockPrescaler(EPWM1_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    //--------------------------------------------------------------------
    //Counter Compare (CC) Module�̐ݒ� �f���[�e�B��̐ݒ�
    //�f���[�e�B��ݒ�AAPI����Ȃ����K�؂ȃf���[�e�B�䂪�ݒ�ł��Ȃ�
    //�b��Ń��W�X�^���ڐݒ�
    //--------------------------------------------------------------------
    //CMPA duty ratio setting is "fixed 50%"
    EPwm1Regs.CMPA.all = (unsigned long)(65536.0 * ((float)EPwm1Regs.TBPRD * EPWM1_PULSEWIDTH_A));
    //EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, (unsigned long)(65536.0 * ((float)EPwm1Regs.TBPRD * EPWM1_PULSEWIDTH_A)));
    //CMPB duty ratio setting is "fixed 50%"
    EPwm1Regs.CMPB.all = (unsigned long)(65536.0 * ((float)EPwm1Regs.TBPRD * EPWM1_PULSEWIDTH_B));
    //EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_B, (unsigned long)(65536.0 * ((float)EPwm1Regs.TBPRD * EPWM1_PULSEWIDTH_B)));

    //CMPA : Enable shadow Register
    EPWM_setCounterCompareShadowLoadMode(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
    //CMPB : Enable shadow Register
    EPWM_setCounterCompareShadowLoadMode(EPWM1_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);

    //--------------------------------------------------------------------
    //Action Qualifier(AQ) Module�̐ݒ�
    //--------------------------------------------------------------------
    EPWM_setActionQualifierAction(EPWM1_BASE,EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(EPWM1_BASE,EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(EPWM1_BASE,EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(EPWM1_BASE,EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

    //--------------------------------------------------------------------
    //Dead Band Generator(DB) Module�̐ݒ�
    //--------------------------------------------------------------------
    //Configure deadband delay mode
    EPWM_setDeadBandDelayMode(EPWM1_BASE, EPWM_DB_RED, true);   //�����オ��G�b�W�ɒx����t������
    EPWM_setDeadBandDelayMode(EPWM1_BASE, EPWM_DB_FED, true);   //����������G�b�W�ɒx����t������
    //Configure deadband delay polarity
    EPWM_setDeadBandDelayPolarity(EPWM1_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);   //�񔽓]
    EPWM_setDeadBandDelayPolarity(EPWM1_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);    //���]
    //Configure inputs for RED & FED delay
    EPWM_setRisingEdgeDeadBandDelayInput(EPWM1_BASE, EPWM_DB_INPUT_EPWMA);
    EPWM_setFallingEdgeDeadBandDelayInput(EPWM1_BASE, EPWM_DB_INPUT_EPWMA);
    //Configure RED & FED delay values
    EPWM_setFallingEdgeDelayCount(EPWM1_BASE, EPWM1_RISE_DB);
    EPWM_setRisingEdgeDelayCount(EPWM1_BASE, EPWM1_FALL_DB);

    //--------------------------------------------------------------------
    //HRPWM Module�̐ݒ�
    //--------------------------------------------------------------------
    //Sets the high resolution comparator load mode.
    //Load from shadow register to active register with TBCTR = 0
    HRPWM_setCounterCompareShadowLoadEvent(EPWM1_BASE, HRPWM_CHANNEL_A,HRPWM_LOAD_ON_CNTR_ZERO);
    HRPWM_setCounterCompareShadowLoadEvent(EPWM1_BASE, HRPWM_CHANNEL_B,HRPWM_LOAD_ON_CNTR_ZERO);
    //Configure MEP edge & control mode for channel A & B. MEP Edge control is on falling edge. Control mode is duty control.
    //��������[�h��K�p����ꏊ(�p���X���ɑ΂��ĂȂ̂��A�ʑ��ɑ΂��ĂȂ̂���ݒ肷��)
    HRPWM_setMEPEdgeSelect(EPWM1_BASE, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE);
    HRPWM_setMEPControlMode(EPWM1_BASE, HRPWM_CHANNEL_A, HRPWM_MEP_PHASE_CTRL);
    HRPWM_setMEPEdgeSelect(EPWM1_BASE, HRPWM_CHANNEL_B, HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE);
    HRPWM_setMEPControlMode(EPWM1_BASE, HRPWM_CHANNEL_B, HRPWM_MEP_PHASE_CTRL);
    //Enable auto-conversion logic.
    //�����ϊ��@�\��L��(��{�I�ɗL���ݒ�)
    HRPWM_enableAutoConversion(EPWM1_BASE);

    //Enable HRPWM phase synchronization on software sync.
    //Required for up-down count HR control..
    //HRPWM_enablePhaseShiftLoad(EPWM1_BASE);

    //--------------------------------------------------------------------
    //ET Module �̐ݒ�
    //--------------------------------------------------------------------
    //EPWM���ADC�̃g���K������܂�
    //ADC �ϊ��J�nA�iEPWMxSOCA�j�p���X�̃C�l�[�u��
    EPWM_enableADCTrigger(EPWM1_BASE, EPWM_SOC_A);
    //�ǂ̃^�C�~���O�ŕϊ��J�nA�p���X��o���� �^�C�}�J�E���^��0�ɂȂ�����
    EPWM_setADCTriggerSource(EPWM1_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO);
    //Sets the ePWM SOC event counts. ����
    EPWM_setADCTriggerEventPrescale(EPWM1_BASE, EPWM_SOC_A, 1);
    //Clear SOC flag.
    EPWM_clearADCTriggerFlag(EPWM1_BASE, EPWM_SOC_A);


    //Timer Starting
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
    EDIS;
}

//*****************************************************************************
// EPWM2�̏�����
// ����D���A���v�pPWM�o�� �p���X����
// ���� �Ȃ�
// �߂�l �Ȃ�
//*****************************************************************************
void InitEPwm2(void){
    EALLOW;

    //Stop PWM Timer PWM���W�X�^�ݒ莞�N���b�N������K����~����
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    //--------------------------------------------------------------------
    //Time-Base(TB) Module�̐ݒ�
    //--------------------------------------------------------------------
    //�ݒ�l�l�𑦔��f����
    EPWM_setPeriodLoadMode(EPWM2_BASE, EPWM_PERIOD_DIRECT_LOAD);
    //�^�C�}�J�E���g�A�b�v
    EPWM_setTimeBaseCounterMode(EPWM2_BASE, EPWM_COUNTER_MODE_UP);
    //PWM�����̐ݒ�
    EPWM_setTimeBasePeriod(EPWM2_BASE, EPWM2_PERIOD - 1);
    //�ʑ��V�t�g���[�h���� EPWM1�Ɠ��������邽��
    EPWM_enablePhaseShiftLoad(EPWM2_BASE);
    //�ʑ��̐ݒ� Master��0��
    EPWM_setPhaseShift(EPWM2_BASE, 0);
    //�J�E���^�l�̃N���A
    EPWM_setTimeBaseCounter(EPWM2_BASE, 0);
    //�����M�����͑I�� PWM1�Ɠ���
    EPWM_setSyncInPulseSource(EPWM2_BASE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);

    //--------------------------------------------------------------------
    //PWM�N���b�N�̕����ݒ�
    //--------------------------------------------------------------------
    EPWM_setClockPrescaler(EPWM2_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    //--------------------------------------------------------------------
    //Counter Compare (CC) Module�̐ݒ� �f���[�e�B��̐ݒ�
    //�f���[�e�B��ݒ�AAPI����Ȃ����K�؂ȃf���[�e�B�䂪�ݒ�ł��Ȃ�
    //�b��Ń��W�X�^���ڐݒ�
    //--------------------------------------------------------------------
    //CMPA�f�B�[�e�B��̐ݒ� 50%�Œ�
    EPwm2Regs.CMPA.all = (unsigned long)(65536.0 * ((float)EPwm2Regs.TBPRD * EPWM2_PULSEWIDTH_A));
    //EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, (unsigned long)(65536.0 * ((float)EPwm1Regs.TBPRD * EPWM1_PULSEWIDTH_A)));
    //CMPB�f�B�[�e�B��̐ݒ� 50%�Œ�
    EPwm2Regs.CMPB.all = (unsigned long)(65536.0 * ((float)EPwm2Regs.TBPRD * EPWM2_PULSEWIDTH_B));
    //EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_B, (unsigned long)(65536.0 * ((float)EPwm1Regs.TBPRD * EPWM1_PULSEWIDTH_B)));

    //CMPA �V���h�E���W�X�^��L���ɂ���
    EPWM_setCounterCompareShadowLoadMode(EPWM2_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
    //CMPB �V���h�E���W�X�^��L���ɂ���
    EPWM_setCounterCompareShadowLoadMode(EPWM2_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);

    //--------------------------------------------------------------------
    //Action Qualifier(AQ) Module�̐ݒ�
    //--------------------------------------------------------------------
    EPWM_setActionQualifierAction(EPWM2_BASE,EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(EPWM2_BASE,EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(EPWM2_BASE,EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(EPWM2_BASE,EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

    //--------------------------------------------------------------------
    //Dead Band Generator(DB) Module�̐ݒ�
    //--------------------------------------------------------------------
    //Configure deadband delay mode
    EPWM_setDeadBandDelayMode(EPWM2_BASE, EPWM_DB_RED, true);   //�����オ��G�b�W�ɒx����t������
    EPWM_setDeadBandDelayMode(EPWM2_BASE, EPWM_DB_FED, true);   //����������G�b�W�ɒx����t������
    //Configure deadband delay polarity
    EPWM_setDeadBandDelayPolarity(EPWM2_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);   //�񔽓]
    EPWM_setDeadBandDelayPolarity(EPWM2_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);    //���]
    //Configure inputs for RED & FED delay
    EPWM_setRisingEdgeDeadBandDelayInput(EPWM2_BASE, EPWM_DB_INPUT_EPWMA);
    EPWM_setFallingEdgeDeadBandDelayInput(EPWM2_BASE, EPWM_DB_INPUT_EPWMA);
    //Configure RED & FED delay values
    EPWM_setFallingEdgeDelayCount(EPWM2_BASE, EPWM2_RISE_DB);
    EPWM_setRisingEdgeDelayCount(EPWM2_BASE, EPWM2_FALL_DB);

    //--------------------------------------------------------------------
    //HRPWM Module�̐ݒ�
    //--------------------------------------------------------------------
    //Sets the high resolution comparator load mode.
    //�V���h�E���W�X�^����A�N�e�B�u���W�X�^��TBCTR=0�Ń��[�h
    HRPWM_setCounterCompareShadowLoadEvent(EPWM2_BASE, HRPWM_CHANNEL_A,HRPWM_LOAD_ON_CNTR_ZERO);
    HRPWM_setCounterCompareShadowLoadEvent(EPWM2_BASE, HRPWM_CHANNEL_B,HRPWM_LOAD_ON_CNTR_ZERO);
    //Configure MEP edge & control mode for channel A & B. MEP Edge control is on falling edge. Control mode is duty control.
    //��������[�h��K�p����ꏊ(�p���X���ɑ΂��ĂȂ̂��A�ʑ��ɑ΂��ĂȂ̂���ݒ肷��)
    HRPWM_setMEPEdgeSelect(EPWM2_BASE, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE);
    HRPWM_setMEPControlMode(EPWM2_BASE, HRPWM_CHANNEL_A, HRPWM_MEP_PHASE_CTRL);
    HRPWM_setMEPEdgeSelect(EPWM2_BASE, HRPWM_CHANNEL_B, HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE);
    HRPWM_setMEPControlMode(EPWM2_BASE, HRPWM_CHANNEL_B, HRPWM_MEP_PHASE_CTRL);
    //Enable auto-conversion logic.
    //�����ϊ��@�\��L��(��{�I�ɗL���ݒ�)
    HRPWM_enableAutoConversion(EPWM2_BASE);

    //�^�C�}�[�X�^�[�g
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
    EDIS;
}

//*****************************************************************************
// EPWM3�̏�����
// ����DCDC�R���o�[�^�pPWM�o�� �t�F�[�Y�V�t�gPWM
// ���� �Ȃ�
// �߂�l �Ȃ�
//*****************************************************************************
void InitEPwm3(void){
    EALLOW;

    //Stop PWM Timer PWM���W�X�^�ݒ莞�N���b�N������K����~����
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    //--------------------------------------------------------------------
    //Time-Base(TB) Module�̐ݒ�
    //--------------------------------------------------------------------
    
    //�ݒ�l�l�𑦔��f����
    EPWM_setPeriodLoadMode(EPWM3_BASE, EPWM_PERIOD_DIRECT_LOAD);
    //�^�C�}�J�E���g�A�b�v
    EPWM_setTimeBaseCounterMode(EPWM3_BASE, EPWM_COUNTER_MODE_UP);
    //PWM�����̐ݒ�
    EPWM_setTimeBasePeriod(EPWM3_BASE, EPWM3_PERIOD - 1);
    //�ʑ��V�t�g���[�h���� EPWM1�Ɠ��������邽��
    EPWM_enablePhaseShiftLoad(EPWM3_BASE);
    //�ʑ��̐ݒ� Master��0��
    EPWM_setPhaseShift(EPWM3_BASE, 0);
    //EPwm2Regs.TBPHS.all = (unsigned long)(65536.0 * ((float)EPwm2Regs.TBPRD * 0.25));
    //�J�E���^�l�̃N���A
    EPWM_setTimeBaseCounter(EPWM3_BASE, 0);
    //�����M�����͑I�� PWM1�Ɠ���
    EPWM_setSyncInPulseSource(EPWM3_BASE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);

    //--------------------------------------------------------------------
    //PWM�N���b�N�̕����ݒ�
    //--------------------------------------------------------------------
    EPWM_setClockPrescaler(EPWM3_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    //--------------------------------------------------------------------
    //Counter Compare (CC) Module�̐ݒ� �f���[�e�B��̐ݒ�
    //�f���[�e�B��ݒ�AAPI����Ȃ����K�؂ȃf���[�e�B�䂪�ݒ�ł��Ȃ�
    //�b��Ń��W�X�^���ڐݒ�
    //--------------------------------------------------------------------
    //CMPA�f�B�[�e�B��̐ݒ� 50%�Œ�
    EPwm3Regs.CMPA.all = (unsigned long)(65536.0 * ((float)EPwm3Regs.TBPRD * EPWM3_PULSEWIDTH_A));
    //EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, (unsigned long)(65536.0 * ((float)EPwm1Regs.TBPRD * EPWM1_PULSEWIDTH_A)));
    //CMPB�f�B�[�e�B��̐ݒ� 50%�Œ�
    EPwm3Regs.CMPB.all = (unsigned long)(65536.0 * ((float)EPwm3Regs.TBPRD * EPWM3_PULSEWIDTH_B));
    //EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_B, (unsigned long)(65536.0 * ((float)EPwm1Regs.TBPRD * EPWM1_PULSEWIDTH_B)));

    //CMPA �V���h�E���W�X�^��L���ɂ���
    EPWM_setCounterCompareShadowLoadMode(EPWM3_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
    //CMPB �V���h�E���W�X�^��L���ɂ���
    EPWM_setCounterCompareShadowLoadMode(EPWM3_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);

    //--------------------------------------------------------------------
    //Action Qualifier(AQ) Module�̐ݒ�
    //--------------------------------------------------------------------
    EPWM_setActionQualifierAction(EPWM3_BASE,EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(EPWM3_BASE,EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(EPWM3_BASE,EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(EPWM3_BASE,EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

    //--------------------------------------------------------------------
    //Dead Band Generator(DB) Module�̐ݒ�
    //--------------------------------------------------------------------
    //Configure deadband delay mode
    EPWM_setDeadBandDelayMode(EPWM3_BASE, EPWM_DB_RED, true);   //�����オ��G�b�W�ɒx����t������
    EPWM_setDeadBandDelayMode(EPWM3_BASE, EPWM_DB_FED, true);   //����������G�b�W�ɒx����t������
    //Configure deadband delay polarity
    EPWM_setDeadBandDelayPolarity(EPWM3_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);   //�񔽓]
    EPWM_setDeadBandDelayPolarity(EPWM3_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);    //���]
    //Configure inputs for RED & FED delay
    EPWM_setRisingEdgeDeadBandDelayInput(EPWM3_BASE, EPWM_DB_INPUT_EPWMA);
    EPWM_setFallingEdgeDeadBandDelayInput(EPWM3_BASE, EPWM_DB_INPUT_EPWMA);
    //Configure RED & FED delay values
    EPWM_setFallingEdgeDelayCount(EPWM3_BASE, EPWM3_RISE_DB);
    EPWM_setRisingEdgeDelayCount(EPWM3_BASE, EPWM3_FALL_DB);

    //--------------------------------------------------------------------
    //HRPWM Module�̐ݒ�
    //--------------------------------------------------------------------
    //Sets the high resolution comparator load mode.
    //�V���h�E���W�X�^����A�N�e�B�u���W�X�^��TBCTR=0�Ń��[�h
    HRPWM_setCounterCompareShadowLoadEvent(EPWM3_BASE, HRPWM_CHANNEL_A,HRPWM_LOAD_ON_CNTR_ZERO);
    HRPWM_setCounterCompareShadowLoadEvent(EPWM3_BASE, HRPWM_CHANNEL_B,HRPWM_LOAD_ON_CNTR_ZERO);
    //Configure MEP edge & control mode for channel A & B. MEP Edge control is on falling edge. Control mode is duty control.
    //��������[�h��K�p����ꏊ(�p���X���ɑ΂��ĂȂ̂��A�ʑ��ɑ΂��ĂȂ̂���ݒ肷��)
    HRPWM_setMEPEdgeSelect(EPWM3_BASE, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE);
    HRPWM_setMEPControlMode(EPWM3_BASE, HRPWM_CHANNEL_A, HRPWM_MEP_PHASE_CTRL);
    HRPWM_setMEPEdgeSelect(EPWM3_BASE, HRPWM_CHANNEL_B, HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE);
    HRPWM_setMEPControlMode(EPWM3_BASE, HRPWM_CHANNEL_B, HRPWM_MEP_PHASE_CTRL);
    //Enable auto-conversion logic.
    //�����ϊ��@�\��L��(��{�I�ɗL���ݒ�)
    HRPWM_enableAutoConversion(EPWM3_BASE);

    //�^�C�}�[�X�^�[�g
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
    EDIS;
}

//*****************************************************************************
// EPWM4�̏�����
// ����DCDC�R���o�[�^�pPWM�o�� �t�F�[�Y�V�t�gPWM
// ���� �Ȃ�
// �߂�l �Ȃ�
//*****************************************************************************
void InitEPwm4(void){
    EALLOW;

    //Stop PWM Timer PWM���W�X�^�ݒ莞�N���b�N������K����~����
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    //--------------------------------------------------------------------
    //Time-Base(TB) Module�̐ݒ�
    //--------------------------------------------------------------------
    //�ݒ�l�l�𑦔��f����
    EPWM_setPeriodLoadMode(EPWM4_BASE, EPWM_PERIOD_DIRECT_LOAD);
    //�^�C�}�J�E���g�A�b�v
    EPWM_setTimeBaseCounterMode(EPWM4_BASE, EPWM_COUNTER_MODE_UP);
    //PWM�����̐ݒ�
    EPWM_setTimeBasePeriod(EPWM4_BASE, EPWM4_PERIOD - 1);
    //�ʑ��V�t�g���[�h���� EPWM1�Ɠ��������邽��
    EPWM_enablePhaseShiftLoad(EPWM4_BASE);
    //�ʑ��̐ݒ� Master��0��
    EPWM_setPhaseShift(EPWM4_BASE, 0);
    //EPwm2Regs.TBPHS.all = (unsigned long)(65536.0 * ((float)EPwm2Regs.TBPRD * 0.25));
    //�J�E���^�l�̃N���A
    EPWM_setTimeBaseCounter(EPWM4_BASE, 0);
    //�����M�����͑I�� PWM1�Ɠ���
    EPWM_setSyncInPulseSource(EPWM4_BASE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);

    //--------------------------------------------------------------------
    //PWM�N���b�N�̕����ݒ�
    //--------------------------------------------------------------------
    EPWM_setClockPrescaler(EPWM4_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    //--------------------------------------------------------------------
    //Counter Compare (CC) Module�̐ݒ� �f���[�e�B��̐ݒ�
    //�f���[�e�B��ݒ�AAPI����Ȃ����K�؂ȃf���[�e�B�䂪�ݒ�ł��Ȃ�
    //�b��Ń��W�X�^���ڐݒ�
    //--------------------------------------------------------------------
    //CMPA�f�B�[�e�B��̐ݒ� 50%�Œ�
    EPwm4Regs.CMPA.all = (unsigned long)(65536.0 * ((float)EPwm4Regs.TBPRD * EPWM4_PULSEWIDTH_A));
    //EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, (unsigned long)(65536.0 * ((float)EPwm1Regs.TBPRD * EPWM1_PULSEWIDTH_A)));
    //CMPB�f�B�[�e�B��̐ݒ� 50%�Œ�
    EPwm4Regs.CMPB.all = (unsigned long)(65536.0 * ((float)EPwm4Regs.TBPRD * EPWM4_PULSEWIDTH_B));
    //EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_B, (unsigned long)(65536.0 * ((float)EPwm1Regs.TBPRD * EPWM1_PULSEWIDTH_B)));

    //CMPA �V���h�E���W�X�^��L���ɂ���
    EPWM_setCounterCompareShadowLoadMode(EPWM4_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
    //CMPB �V���h�E���W�X�^��L���ɂ���
    EPWM_setCounterCompareShadowLoadMode(EPWM4_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);

    //--------------------------------------------------------------------
    //Action Qualifier(AQ) Module�̐ݒ�
    //--------------------------------------------------------------------
    EPWM_setActionQualifierAction(EPWM4_BASE,EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(EPWM4_BASE,EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(EPWM4_BASE,EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(EPWM4_BASE,EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

    //--------------------------------------------------------------------
    //Dead Band Generator(DB) Module�̐ݒ�
    //--------------------------------------------------------------------
    //Configure deadband delay mode
    EPWM_setDeadBandDelayMode(EPWM4_BASE, EPWM_DB_RED, true);   //�����オ��G�b�W�ɒx����t������
    EPWM_setDeadBandDelayMode(EPWM4_BASE, EPWM_DB_FED, true);   //����������G�b�W�ɒx����t������
    //Configure deadband delay polarity
    EPWM_setDeadBandDelayPolarity(EPWM4_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);   //�񔽓]
    EPWM_setDeadBandDelayPolarity(EPWM4_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);    //���]
    //Configure inputs for RED & FED delay
    EPWM_setRisingEdgeDeadBandDelayInput(EPWM4_BASE, EPWM_DB_INPUT_EPWMA);
    EPWM_setFallingEdgeDeadBandDelayInput(EPWM4_BASE, EPWM_DB_INPUT_EPWMA);
    //Configure RED & FED delay values
    EPWM_setFallingEdgeDelayCount(EPWM4_BASE, EPWM4_RISE_DB);
    EPWM_setRisingEdgeDelayCount(EPWM4_BASE, EPWM4_FALL_DB);

    //--------------------------------------------------------------------
    //HRPWM Module�̐ݒ�
    //--------------------------------------------------------------------
    //Sets the high resolution comparator load mode.
    //�V���h�E���W�X�^����A�N�e�B�u���W�X�^��TBCTR=0�Ń��[�h
    HRPWM_setCounterCompareShadowLoadEvent(EPWM4_BASE, HRPWM_CHANNEL_A,HRPWM_LOAD_ON_CNTR_ZERO);
    HRPWM_setCounterCompareShadowLoadEvent(EPWM4_BASE, HRPWM_CHANNEL_B,HRPWM_LOAD_ON_CNTR_ZERO);
    //Configure MEP edge & control mode for channel A & B. MEP Edge control is on falling edge. Control mode is duty control.
    //��������[�h��K�p����ꏊ(�p���X���ɑ΂��ĂȂ̂��A�ʑ��ɑ΂��ĂȂ̂���ݒ肷��)
    HRPWM_setMEPEdgeSelect(EPWM4_BASE, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE);
    HRPWM_setMEPControlMode(EPWM4_BASE, HRPWM_CHANNEL_A, HRPWM_MEP_PHASE_CTRL);
    HRPWM_setMEPEdgeSelect(EPWM4_BASE, HRPWM_CHANNEL_B, HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE);
    HRPWM_setMEPControlMode(EPWM4_BASE, HRPWM_CHANNEL_B, HRPWM_MEP_PHASE_CTRL);
    //Enable auto-conversion logic.
    //�����ϊ��@�\��L��(��{�I�ɗL���ݒ�)
    HRPWM_enableAutoConversion(EPWM4_BASE);

    //�^�C�}�[�X�^�[�g
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
    EDIS;
}

//*****************************************************************************
// CLA��������x����p
//*****************************************************************************
void InitEPwm12(void){
    EALLOW;

    //Stop PWM Timer PWM���W�X�^�ݒ莞�N���b�N������K����~����
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    //Setup TBCLK
    EPWM_setPeriodLoadMode(EPWM12_BASE, EPWM_PERIOD_DIRECT_LOAD);
    //PWM�����̐ݒ�
    EPWM_setTimeBasePeriod(EPWM12_BASE, 0xffff);
    //�ʑ��̐ݒ� Master��0��
    EPWM_setPhaseShift(EPWM12_BASE, 0);
    //�J�E���^�l�̃N���A
    EPWM_setTimeBaseCounter(EPWM12_BASE, 0);
    //�^�C�}�J�E���g�A�b�v
    EPWM_setTimeBaseCounterMode(EPWM12_BASE, EPWM_COUNTER_MODE_UP);
    //�ʑ��V�t�g���[�h���� EPWM1�Ɠ��������邽��
    EPWM_enablePhaseShiftLoad(EPWM12_BASE);
    //�����M�����͑I�� PWM1�Ɠ���
    EPWM_setSyncInPulseSource(EPWM12_BASE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);

    //--------------------------------------------------------------------
    //PWM�N���b�N�̕����ݒ�
    //--------------------------------------------------------------------
    EPWM_setClockPrescaler(EPWM12_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    //�^�C�}�[�X�^�[�g
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    EDIS;
}

). Can we have your Expert's advice/comments on this, please?

Best regards,

Miyazaki

over 4 years ago

0 Nima Eskandari over 4 years ago

TI__Guru 52040 points

At run time, do you change the CMPx values?

Also can you please tell me are you using high resolution phase shift between the EPMW modules?

HRPWM_setMEPControlMode(EPWM1_BASE, HRPWM_CHANNEL_A, HRPWM_MEP_PHASE_CTRL);
HRPWM_setMEPControlMode(EPWM1_BASE, HRPWM_CHANNEL_B, HRPWM_MEP_PHASE_CTRL);

Also can you in a short description tell me the features in EPWM you are using so I can cross check them with the code?

EPWM in UP mode

PERIOD load is DIRECT

HR mode enabled

HR Phase mode

Anything else I am missing?

0 Takayuki Miyazaki over 4 years ago in reply to Nima Eskandari

TI__Genius 10120 points

Hello Nima,

We are asking customer your questions. when we will receive their feedback, I'll share them as soon as possible.

Best regards,

Miyazaki

0 Takayuki Miyazaki over 4 years ago in reply to Takayuki Miyazaki

TI__Genius 10120 points

Hi Nima,

I received customer feedback.

> At run time, do you change the CMPx values?

Yes, customer is changing CMPA/CMPB during operation. CMPx value is set from “0” to a 50 % Duty-ratio. Normally, since customer is using Phase-Shift-PWM, it is operated with 50% duty ratio. When stopping the PWM, CMPx is set to “0” and PWM-A/PWM-B output are fixed to logical value.

> Also can you please tell me are you using high resolution phase shift between the EPMW modules?

Yes, customer is using HR phase shift. EPwm2 synchronizes with EPwm1

Customer’s configuration is as follows.

EPWM in UP mode

PERIOD load is DIRECT

High Resolution mode

HR Phase mode

Synchronization Mod is Enabled :when the counter of PWM1=0y, other PWM is synchronized.

A 100kHz output PWM waveform is generated.

I’m sorry. I just translated customer’s comments in English. I hope these information includes some hints of solution.

Best regards,

Miyazaki

0 Nima Eskandari over 4 years ago in reply to Takayuki Miyazaki

TI__Guru 52040 points

Are you aware that the HR module is not supposed to be used with less than 3 cycle duty close to the PRD and ZERO?

0 Nima Eskandari over 4 years ago in reply to Nima Eskandari

TI__Guru 52040 points

I looked over your code again as well and it seems like you want to do BOTH EDGE (rising and falling) using HRPWM in UP-MODE.

Thats not supported, you can only control one edge in CTR=UP-Mode, you need to be running in UP-DOWN mode if you want to use the BOTH EDGE control mode.

Nima

0 Takayuki Miyazaki over 4 years ago in reply to Nima Eskandari

TI__Genius 10120 points

Hello Nima,

Thank you for your advice. Regarding the limitation of “less than 3 cycle duty”, I received customer's feedback, just now. customer was trying to check this with their system. As the result, customer was able to notice that their firmware sometime set less than 3 cycle duty. Customer fixed this configuration and confirmed this issue was fixed.

I really appreciate your help.

Best regards,

Miyazaki

C2000™︎ microcontrollers

C2000 microcontrollers forum

CCS/TMS320F28379D: Phase-shift PWM