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Compiler/TMS320F28377D-EP: McBSP configuration as SPI to interface to SSI Sensor

Part Number: TMS320F28377D-EP

Tool/software: TI C/C++ Compiler

Hi Team,

Good day, we received query from our customer and and want to ask support about TMS320F28377D-EP. For me to not miss any information, Ill copy the query below.


I want to interface an SSI Sensor to the McBSP port of TMS320F28377D-EP.
I would to use the SN65HVD30MDREP to interface the MCU to the Sensor. Is it correct?
I would to use McBSP port in SPI mode (the other SPIs ports of the MCU are used for other peripherals) CLOCK signal is master from MCU (MCLKXx), while DATA are transmitted from Encoder to MCU (MDRx). Is it correct?
With reference to attached image, synchronous SSI uses a clock sequence from the MCU to initiate the transmission of data from the sensor (a Read Cycle).
Starting from t=0, after about 25 microseconds, the DATA line will be HIGH indicating a new Read Cycle can be started; at this point, the first falling edge starts the Read Cycle and the transfer of data.
Each rising edge of the CLOCK transmits the next data bit of the message, starting from D31 downto D0.
After the last rising edge of the clock sequence, the data line is set by the Error Flag.

I need to know if the McBSP port is correctly configured for my application (In this moment I cannot try it):

McbspaRegs.SPCR1.bit.DLB = 0;
McbspaRegs.SPCR1.bit.CLKSTP = 2;
McbspaRegs.PCR.bit.CLKXP = 1;
McbspaRegs.PCR.bit.CLKRP = 0;
McbspaRegs.RCR2.bit.RDATDLY =01;
McbspaRegs.XCR2.bit.XDATDLY =01;
McbspaRegs.RCR1.bit.RWDLEN1 =32;
McbspaRegs.XCR1.bit.XWDLEN1 = 0;
McbspaRegs.SRGR2.all= 0x2000;
McbspaRegs.SRGR1.all= 0x0004;


I do not know how to handle the ERROR FLAG"

Thank you and looking forward for your kind response.



  • Maynard,

    I need some time to look into this a bit more, I'll reply back tomm with what I'm able to figure out.


  • Maynard,

    I agree with the settings for using the McBSP as SPI Master.  I don't know the specs on the DS for the SSI sensor, but I did notice that customer has selected negative polarity for the TX, which could be fine I just don't have the details on what the other IC is expecting.

    I don't know how to handle the "error" bit either; I would assume most SPI implementations cap at 32-bits or at least an even number of bits; so I'm not sure why it is reasonable to expect an odd extra bit to be generated....