Hi Champ,
Customer used 20M Crystal and the load capacitance is 8pf.
but from datasheet the MIN value should be 12pf, any risk for case use case?
what is our suggestion?
,使用的外部电容为两个8pf
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Hi Champ,
Customer used 20M Crystal and the load capacitance is 8pf.
but from datasheet the MIN value should be 12pf, any risk for case use case?
what is our suggestion?
,使用的外部电容为两个8pf
Hi Chen,
It depends. Did you customer do any evaluation for the board in terms of crystal start-up time, drive-level, margin etc?
Hi Frank,
Please advise the detail, it is depends on which condition?
If depends , why datasheet MIN value is 12pf?
What the means of drive-level, margin?
Chen,
By the letter of the datasheet, yes this is a violation but it depends on how much stray/parasitic capacitance the PCB is contributing to the effective load capacitance. This is the reason why I asked if your customer did any crystal evaluation on the PCB?
Frank,
Customer used 8uf on current PCB , and the board worked well!
customer just worry about any risk?
Please advise the detail testing that customer need to do?
Chen,
As mentioned in the datasheet, our recommendation to customers is to have the crystal vendor characterize the crystal with their board to see how much margin is left in the system. PCB parasitics has a big effect on crystal performance so just because a crystal worked on one PCB design doesn't necessarily mean it will work on another.
The reason we recommend customers have the crystal vendor perform this evaluation is because most customers don't have the tools or expertise to do this, in particular finding the exact specifications of the crystal in question. Since TI is not a crystal vendor, we cannot do this for a customer.