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TMS320F28377D: Read another core peripheral directly

Janet Shen
Expert 7795 points
Part Number: TMS320F28377D

Dear Champs,

Could you kindly help double confirm below use case?

If we use CPU1 control QEP, could we let CPU2 "read only" the register values of QEP rather than using IPC?

Because customer hope to save the time latency of QEP on CPU2. 

If you have any suggestions, please feel free to let me know.

Thanks a lot.

  • 0
    TI__Guru** 113745 points

    Hi Janet,

     If we use CPU1 control QEP, could we let CPU2 "read only" the register values of QEP rather than using IPC?

    No, CPU2 can not read the register of QEP in this case. It has to be passed from CPU1 via IPC to CPU2.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Expert 7795 points

    Dear Vivek,

    We also tried to use GS RAM to copy the register value from CPU1 to CPU1, but it still need some time.

    If customer hope to save the time latency of QEP on CPU2, how can we do? 

    Or we all need IPC on any way?

    Thanks a lot. 

  • 0 in reply to Vivek Singh
    TI__Expert 7795 points

    Dear Vivek,

    Could you kindly give me any suggestions for saving time latency of "Only Read another core peripheral"?

    Is using GS RAM? 

    If you have any suggestions, please feel free to let me know.

    Thanks a lot.

  • 0 in reply to Janet Shen
    TI__Guru** 113745 points

    Janet,

    Yes, customer can use the GSx RAM to store the read value from CPU1 and then CPU2 can access it but it'll have same latency as via IPC (using MSG RAM). I don't think we have any other way around for this.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Expert 7795 points

    Dear Vivek,

    Understood.

    I will communicate with customer to discuss the effect of the time delay.

    If there still is any concerns, will post a related question to team. 

    Thanks a lot.