TMS320F280049: The difference between two sets of CAN bit timing configurations

Hi Sheldon,

To make the CAN bit timing setup easier for the customer, this calculator was created and it only requires minimal input that is relevant to the customer, like the desired bit rate, CAN clock rate, the CAN bus length and the estimated propagation delay contributed by their choice of transceiver and associated circuits.  The calculator then outputs the values to in the format that is directly written to the CAN bit timing register and the allowable oscillator tolerance based on these 4 key inputs.

The first configuration is obviously derived for 500kbps CAN bit rate, bus length of 50m, estimated extra propagation delay of 0.1us due to transceiver circuit design and assumed CAN clock rate of 100MHz.  Not sure about the second configuration, but I am assuming that customer may have chosen a different bus length, a different estimate for extra propagation delay, and maybe different CAN clock assumption.

The oscillator tolerance reported by the calculator is a guidance on how far the clock on the F280049 device can deviate for the desired CAN bit rate.  For the case of the first configuration derived by the customer, it means that CAN clock will vary from 99MHz to 101Mhz and still transact CAN communications at 500kbps without errors on a 50m CAN bus.  If you try to input 1Mbps to the calculator without modifying the bus length and the extra prop delay, the reported oscillator tolerance drops down to 0.38% which is very tight (clock can only vary within 99.62MHz to 100.38MHz in order to attain 1Mbps CAN bit rate over 50m bus length).  Just provided these comparisons to illustrate the significance of oscillator tolerance in this text.  You can try experimenting with other values of bus length, CAN clock and CAN bit rate and see how the oscillator tolerance changes.

The sampling point is where CAN senses the signal and decides if the value is dominant (0) or recessive (1).  For example, in the first configuration the sampling point reported is at 70%.  What this means is that the signal measurement point is at 70% of the bit width.  Bit width is simply the reciprocal of bit rate (1/500kbps), which is 2us.  For the first configuration, the sampling point is at 0.7*2uS, or 1.4uS.  You can refer to the bit timing figure in section 26.13.1 (Bit Time and Bit Rate) section of the TRM for an illustration on the sampling point and how the prop_seg, Tseg1 (phase_seg1) and Tseg2 (phase_seg2) reported by the bit timing calculator comes into play.

Hope this helps and let me know if you still have questions on this topic.

Best regards,

Joseph 

Hi Joseph,

Thanks for your explanation. Here are some related questions:

1. Bit time can be divided into four parts, take that we received an "active" bit, will an "acive" voltage level be sampled by all these four parts?

2. Based on question one, how will this bit be judged as valid? (how does it related to these four parts?)

3. Is "Prop_Seg" configurable by registers? (In which register sets?)

4. Based on question three, how do we calculate Prop_seg from resgister settings? 

5. How do we decide a suitable sample point?

Thanks

Sheldon