Hi,
I am using trip-zone for pwm in one of my application.
Below is the code what I am using to configure my PWM.
GPIO_PWMconfig(void)
{
// Using GPIO12 as TZ1 pin
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (TZ1)
GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Asynch input GPIO12 (TZ1)
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as TZ1
// Using GPIO_0 as my configuration for PWM
GPIO_setPullUp(GpioHandle, GPIO_Number_0, GPIO_PullUp_Enable);
GPIO_setMode(GpioHandle, GPIO_Number_0, GPIO_0_Mode_EPWM1A);
EALLOW;
EPwm1Regs.TZSEL.bit.CBC1 = 1;
//EPwm1Regs.TZSEL.bit.CBC2 = 1;
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
//EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
//
// Enable TZ interrupt
//
EPwm1Regs.TZEINT.bit.CBC = 1;
EDIS;
EALLOW;
SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // EPWM1
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Enable TBCLK within the EPWM
EPwm1Regs.TBPRD = 6000; // Set timer period
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Slow just to observe on the scope
//
// Setup compare
//
EPwm1Regs.CMPA.half.CMPA = 0;
//
// Set actions
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
EPwm1Regs.AQCTLB.bit.CAD = AQ_SET;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the EPWM
EDIS;
PIE_enableInt(PieHandle, PIE_GroupNumber_2, PIE_InterruptSource_TZ1);
PIE_enablePwmTzInt(PieHandle, PWM_Number_1);
PIE_registerPieIntHandler(PieHandle, PIE_GroupNumber_2, PIE_SubGroupNumber_1,
(intVec_t)&epwm1_tzint_isr);
CPU_enableInt(CpuHandle, CPU_IntNumber_2);
PieCtrlRegs.PIEIER2.bit.INTx1 = 1;
}
/* This is enabling PWMs */
void EnablePwm(void)
{
EPwm1Regs.AQCSFRC.bit.CSFA = 0; // Disable force low
}
/* This is for disabling PWMs */
void DisablePwm(void)
{
EPwm1Regs.AQCSFRC.bit.CSFA = 1; // Enable force low
}
__interrupt void epwm1_tzint_isr(void)
{
//
// Clear the flags - we will continue to take this interrupt until the TZ
// pin goes high
//
EPwm1Regs.TZCLR.bit.CBC = 1;
EPwm1Regs.TZCLR.bit.INT = 1;
//
// Acknowledge this interrupt to receive more interrupts from group 2
//
PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
}
This is very much similar to the example code which is there in C2000 folder.
This code indivually works well as the example code.
When I integrate it with I don't find it working.
For your reference also i have attached the memory allocation for the controller what I have done.
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
PRAML0 : origin = 0x008000, length = 0x000800 /* on-chip RAM block L0 */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASH : origin = 0x3F0000, length = 0x007F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
DRAML1 : origin = 0x3F8000, length = 0x001000
DRAML0 : origin = 0x008800, length = 0x000600
CNTL2P2ZRAM : origin = 0x008E00, length = 0x000060
CNTL2P2ZBUFF: origin = 0x008EC0, length = 0x000060
PWMDRVRAM : origin = 0x008F20, length = 0x000040
ADCDRVRAM : origin = 0x008F60, length = 0x000020
dataRAM : origin = 0x008F80, length = 0x000080
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASH, PAGE = 0
.pinit : > FLASH, PAGE = 0
.text : > FLASH, PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASH,
RUN = PRAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL_P0 PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
ISRvariables :> dataRAM PAGE = 1
ADCDRV_5ch_Section :> ADCDRVRAM PAGE = 1
ZeroNet_Section :> dataRAM PAGE = 1
CNTL_2P2Z_Section :> CNTL2P2ZRAM PAGE = 1
CNTL_2P2Z_InternalData :> CNTL2P2ZBUFF PAGE = 1
CNTL_2P2Z_Coef :> dataRAM PAGE = 1
PWRCAL_Section :> dataRAM PAGE = 1
Fdb_Section :> dataRAM PAGE = 1
FREQDRV_FBINV_Section :> PWMDRVRAM PAGE = 1
/* Allocate uninitalized data sections: */
.stack : > RAMM0 PAGE = 1
.ebss : > DRAML1 PAGE = 1
.esysmem : > DRAML0 PAGE = 1
.sysmem : > DRAML0 PAGE = 1
.cio : >> RAMM0 | RAMM1 | DRAML0 PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASH PAGE = 0
.switch : > FLASH PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASH PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
}
