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Hi
I am designing a secondary boot-loader to flash data over a serial protocol. I am using the Flash API driver to accomplish this.
My controller is dual core - with 512KB flash memory for each.
Is it possible to have my application code on CPU2's flash memory & the secondary boot-loader on CPU1's flash memory? (i.e. can we flash the cpu2's memory from the secondary boot-loader in cpu1's flash memory?)
Can we make use of IPC to serve this purpose?
Thanks
Sayali,
Each core has to program it's own bank. CPU1 can not program CPU2's flash bank. I think you know this. Wanted to confirm.
If you want to keep the boot-loader in CPU1's flash memory and transfer the CPU2 image from CPU1 to CPU2 via IPC - that is fine.
If you want to reduce complication of hand shaking between the two cores, and if you can accommodate CPU2's custom boot-loader in CPU2's flash bank, then it might be easy for you to implement (CPU2's custom loader to reside in CPU2's flash bank).
Hope you already looked at https://www.ti.com/lit/sprabv4
Thanks and regards,
Vamsi
Hi
Yes, I'm aware of the bank allocation scheme. But just wanted to confirm.
Thanks
Sayali,
Ok, I am closing this post. If you have further questions, you can open a new post.
Thanks and regards,
Vamsi