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Hello,
I would like to debug the application on CPU1, and want to reset/run CPU2 from its program already loaded in Flash. Is there an example of how to do this?
Looking at led_ex1_blinky_cpu1 and led_ex1_blinky_cpu2:
And I tried
I'm using Code Composer Studio 10.3.1 and run debug debug configuration.
Hello Amy,
To clarify, you're trying to run each CPU with its respective program but you only want to debug/step through the program on CPU1, correct?
If this is the case, then you can start by debugging the CPU1 program, connecting to the CPU2 target and loading its respective .out file, click the Resume button, and then go back to CPU1 to step through it. You'll still be running both in 'debug mode', but this will allow you to run the CPU2 while debugging CPU1. Whenever you are running from both CPUs, you will need to connect to CPU1, load its .out, connect to CPU2, and load its .out file. If you have the IPC set up properly so that there is a handshake at the beginning of the code between both CPUs, then they should be able to run without issue (although this is only necessary if they are sharing data or need to work in synchronicity).
Best regards,
Omer Amir
Hello Omer,
Thank you so much for your response.
Yes, I would like to run each CPU with its respective program and would like to debug CPU1.
I have data share memory between CPU1 and CPU2. I can debug CPU2 just fine, but whenever I try to step/debug CPU1, then CPU2 stop run.
Hello Amy,
Can you clarify what you mean by CPU2 stops running? I need more precise detail on what's happening.
Best regards,
Omer Amir
Hi Omer,
Sorry, I mean the CPU2 not update values when I looked at the those variables in the debug.
Also, I see the message in the debug showed
"C28xx_CPU2: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. Also, CPU1 will be halted to determine SR ownership for the CPU which will run the Flash Plugin code, after which CPU1 will be set to run its application. User code execution from SR could commence after both flash banks are programmed.
C28xx_CPU1: GEL Output:
Memory Map Initialization Complete
C28xx_CPU2: GEL Output:
Memory Map Initialization Complete"
Is there a way to debug/steps through both CPU1 and CPU2. Or just looked at the global variables in the CPU2 while debug CPU1?
Hello Amy,
Is there a way to debug/steps through both CPU1 and CPU2. Or just looked at the global variables in the CPU2 while debug CPU1?
No, there is not. If you are debugging/running both CPUs they can only be stepped through one-at-a-time (they can both be running or in debug mode, but you can only view changes to one of them at a time). When you're trying to look at the variables changing in CPU2 in debug mode, are you still stepping through the CPU1 code? If so, then this is why you are not seeing any updates. The CPUs do not communicate their data together through the debugger, you will need to use IPC if you wish to see variables from both CPUs changing. The values do not update/change unless you connect to that CPU so the debugger can view that program.
Best regards,
Omer Amir
Hello Omer,
I see both CPU1 and CPU2 using share memory in data section using
#pragma DATA_SECTION(data_state2,"SHARERAMGS1");
#pragma DATA_SECTION(data_state1,"SHARERAMGS0");
Is there a way to see the data SHARERAMGS1 SHARERAMGS0 of CPU2 when in the debug of CPU1?
Or is there a way to print data in CPU2 while debug CPU1?
Hello Amy,
Is there a way to see the data SHARERAMGS1 SHARERAMGS0 of CPU2 when in the debug of CPU1?
You can view the memory using the Memory Browser window in CCS. If this is a shared memory and CPU2 modifies it, it should be updated.
Or is there a way to print data in CPU2 while debug CPU1?
I'm sure there is, but I do not think it will show up on the console if you're currently connected to CPU1 (it may or may not, you can test this to find out). The best way to monitor the status of variables between CPUs is using the Inter-Processor Communication module (IPC). Please refer to the technical reference manual for more details.
Best regards,
Omer Amir