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Original question:

TMS320F28377D-EP: Local Shared Ram access arbitration

TMS320F28377D: GSRAMx access from both CPU1 and CPU2

Etiam
Intellectual 730 points
Part Number: TMS320F28377D

Hello,

I need to share some variable between CPU1 and CPU2, and the problem is that both CPUs can modify this value. I was wondering on doing something similar like the example of RAM management, declaring in each CPU project one variable for R&W operations and another only for R operations.

My question is: in this example, the use of IPC flags between CPUs is mandatory in order to control that both CPUs don't try to access at the same time in one RAM sector (p.ex CPU1 to write and CPU2 to read)? Do I understand well? 

This example of RAM management in fact duplicates the memory space needed for the application. Is there another way to share variables between both CPUs without duplicating variables if both CPUs need to R&W to theses variables? 

Then, IPC API drivers only work with IPC Message RAM memory? Not for GSxRAM memory? In that case, what are the advantages of using IPC API drivers if I don't need more memory from GSxRAM?

Thank you

  • 0
    TI__Guru** 113715 points

    Hi,

    My question is: in this example, the use of IPC flags between CPUs is mandatory in order to control that both CPUs don't try to access at the same time in one RAM sector (p.ex CPU1 to write and CPU2 to read)? Do I understand well? 

    IPC is needed to sequence the operation. E.g. to make sure CPU which is reading only reads after variable has been updated. In general HW supports both access at same time and arbitrate the access based on round-robin method.

    This example of RAM management in fact duplicates the memory space needed for the application. Is there another way to share variables between both CPUs without duplicating variables if both CPUs need to R&W to theses variables? 

    This example shows our recommendation. There may be other ways too. Both CPU can not do R&W to same memory location. Only master CPU has write access. Not sure if I understand this query.

    Then, IPC API drivers only work with IPC Message RAM memory? Not for GSxRAM memory? In that case, what are the advantages of using IPC API drivers if I don't need more memory from GSxRAM?

    I would assume driver should work for GSx RAM too but need to check with our SW team but if are only sharing small data then message RAM is better to use.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Guru 53105 points

    Seconding Vivek's answer to your last question--I'm not sure if the IPC drivers have been tested for use with GSxRAM locations instead of message RAM locations, but I don't see anything in the code that would prevent you from using it that way as long as you have your RAM sections' master configured appropriately.

    Whitney