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TMS320F2808: F2808 SPI timing

Bob Bacon
Genius 10815 points
Part Number: TMS320F2808
Other Parts Discussed in Thread: ADS8319

Hello
My customer is trying to interface an ADS8319 running at 10MHz clock speed to the F2808 using SPI.
Although this appears to work OK they are checking that the timing meets all min / max cases and have come across a problem that I am hoping you might be able to offer some suggestions / advice.

They tell us

The ADS8319, has SDI strapped high, so is configured for what is referred to as "/CS Mode", and has VBD set to 3.3V. From the ADS8319 data sheet, in this configuration, the ADS8319 changes data following the falling edge of the SPICLK, with a minimum Data Hold time of 5ns. (t2 of datasheet SLA600C table 7.7)

 

The next data bit is established some time later, this time being influenced by the device VBD being 3.3V, so 7.7 (SLA600C) is referenced, and this indicates that new data is valid after a maximum delay of 24ns from the same clock edge.

 

We have the TMS320 values set as follows:

 

    • LSPCLK frequency of 50MHz, tC(LCO) = 20ns
    • SPICLK frequency of 10MHz, tC(SPC)M = 100ns
    • Clock Polarity =0
    • Clock Phase = 0

 

And therefore from the TMS320 datasheet the required hold time from Table 6-34. SPI Master Mode External Timing (Clock Phase = 0) is 30ns.

 

0.5*10050ns – 0.5*20ns – 10ns = 30ns minimum data hold timemaximum

 

 

This means that following the falling edge we potentially loose the valid data after 5ns but are required to maintain this for up to 30ns for the TMS320 to acquire the sample.

 

From testing it looks like we are not seeing a problem so far as I would expect to see this present on all bit reads MSB to LSB . Hence either we get valid data or a gross error (please comment). We have seen the ADC hold time (t2 of datasheet SLA600C table 7.7) from negative clock edge to ADC data held as approximately 10ns with a successful read by the TMS 320. Hence well within the maximum but far short of the 30ns quoted.

 

In order to understand this in slightly more detail, we would be interested in what defines the hold valid parameter tv(SPCL-SOMI)M . Further:

 

    • Is the value 30ns an extreme case defined as a sigma type parameter
    • Is there a typical value which is in keeping with what we observe
    • If the data was not held valid prior to TMS320 data read, is it right to predict a gross error (which would be detected).
    • While our unit is working with 10ns, might problems arise if the ADS did only satisfy its data Hold minimum of 5ns?

 

 

Best Regards

Bob Bacon

  • 0
    Guru 30330 points
    Bob,

    We are aware of some issues with the SPI timings and are working on updating the tables.
    To answer your questions, the SOMI hold time minimum value is 0ns. If the slave data is not held up until the capture edge, the data may be incorrect.

    We will update the tables as we have confirmation.
  • 0 in reply to Mark Labbato
    TI__Genius 10815 points

    Hi Mark

    Incidentally, looking at TMS320x280x, 2801x, 2804x Serial Peripheral Interface Reference Guide, SPRUG72–February 2009, I have a query relating to two observations concerning documentation.

    Is there an errata/addendum that I’ve overlooked for the document, perhaps an errata against the TMS320 itself that covers issues licked up in other parts of the documentation suite?

    For example, section 2.1.1 SPICCR bit 4 (SPILBK) is shown as R-0, but appears to be the only way to select Loopback, so I presume it should be R/W-0.

    section 2.1.3 shows three bits listed as R/C-0 but this isn’t listed in the LEGEND beneath.  In this case, table 2-4 clearly details that the process of writing to the register with bit 7 set to 1 causes the corresponding bit to be Cleared, but the other bits don’t seem to be affected by a Write, so should they be R-0?

    Many Thanks

    Bob Bacon

  • 0 in reply to Bob Bacon
    Guru 30330 points
    Hi Bob,

    The Errata document for the F2804x devices is located here: www.ti.com/.../sprz255 . Generally, we do not file update the errata for User Guide errors or examples.

    SPICCR.SPILBK is in fact a R/W -0 type bit. You are correct that SPILBK controls the loopback functionality.

    Regarding the "R/C-0" bits, this means Read/Write 1 to Clear - reset state is 0. The correct descriptions are:
    SPIST.7 -- R/C - 0
    SPIST.6 -- R - 0
    SPIST.5 -- R - 0
    SPIST.4-0 -- R - 0

    I will file tickets to get these bit descriptions corrected. Thank you for the feedback.
  • 0 in reply to Mark Labbato
    TI__Genius 10815 points

    Hello
    Do you have an estimate of when an updated Data Sheet will be released with these corrections ?

    Thanks

    Bob Bacon

  • 0 in reply to Bob Bacon
    TI__Genius 10815 points

    Hello
    My Customer has an additional question

    Apologies, but one aspect that I didn’t spot before, which we could do with clarifying quickly is that the table you offered (four tabs, covering the four clocking schemes) now no longer mentions which SPICLK edge the timings are in relation to.

     

    It appears that there is inconsistent data between TI documents; according to SPRUG72, (the SPI details for the TMS320), the data concerning the SPI Clocking schemes is summarised in Table 1-3:   

    Rising edge without delay is selected with SPICCR.6 = 0 and SPICTL.3 = 0

     

    However, in SPRS230N (TMS320) SPI section 6.10.5, table 6-34 (row “5”), my reading of it suggests that the data is strobed around the SPICLK falling edge when Clock Polarity is 0, and the rising edge when Clock Polarity is 1.

     

    Can you clarify the correct interpretation of these bits and the clocking scheme selection, and add which clock edges are relevant in the “in review” spreadsheet that you supplied?

     

    Many Thanks
    Bob Bacon

  • 0 in reply to Bob Bacon
    Guru 30330 points
    Bob,

    We are working on the timeline for the datasheet release now. The tables have been finalized and shared with you offline.

    Reading the full section 1.4.3.1 SPI Clocking Schemes, the combination of the text at the beginning of that section plus the Figure 1-4 SPICLK Signal Options, it shows where the data is transmitted and the “strobe” edge of each configuration. I am not quite sure where the confusion lies. For Table 6-34, SPISIMO is latched (transmitted) on the rising edge when Polarity = 0, or falling edge when Polarity = 1 (parameter 4). SPISOMI is strobed (received) on the Falling edge when Polarity is 0, or rising edge when polarity is 1.

    Regards,
    Mark