CCS/TMS320F28379D: Trigger CLA using ePWM interrupts

Tool/software: Code Composer Studio

Hi!

I am wondering how to link the interrupt from my ePWM to be able to trigger my CLA interrupt. I've been studying examples in ControlSuite but I doesn't seem to find an CLA example with ePWM triggered tasks. Before I was using the ePWM interrupt in CPU1 to perform the task but now I want faster performance.

From my ePWM1 I have this to trigger an interrupt:

EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Trigger INT on at Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on N'th event

and here is my CLA configuring code (it's basically copied from an example):

void CLA_configClaMemory(void)
{
extern uint32_t Cla1funcsRunStart, Cla1funcsLoadStart, Cla1funcsLoadSize;
EALLOW;

#ifdef _FLASH
//
// Copy over code from FLASH to RAM
//
memcpy((uint32_t *)&Cla1funcsRunStart, (uint32_t *)&Cla1funcsLoadStart,
(uint32_t)&Cla1funcsLoadSize);
#endif //_FLASH

//
// Initialize and wait for CLA1ToCPUMsgRAM
//
MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1){};

//
// Initialize and wait for CPUToCLA1MsgRAM
//
MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1){};

//
// Select LS5RAM to be the programming space for the CLA
// First configure the CLA to be the master for LS5 and then
// set the space to be a program block
//
MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;

//
// Next configure LS0RAM and LS1RAM as data spaces for the CLA
// First configure the CLA to be the master for LS0(1) and then
// set the spaces to be code blocks
//
MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0;

MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0;

EDIS;
}

//
// CLA_initCpu1Cla1 - Initialize CLA1 task vectors and end of task interrupts
//
void CLA_initCpu1Cla1(void)
{
//
// Compute all CLA task vectors
// On Type-1 CLAs the MVECT registers accept full 16-bit task addresses as
// opposed to offsets used on older Type-0 CLAs
//
EALLOW;
Cla1Regs.MVECT1 = (uint16_t)(&Cla1Task1);
Cla1Regs.MVECT2 = (uint16_t)(&Cla1Task2);
Cla1Regs.MVECT3 = (uint16_t)(&Cla1Task3);
Cla1Regs.MVECT4 = (uint16_t)(&Cla1Task4);
Cla1Regs.MVECT5 = (uint16_t)(&Cla1Task5);
Cla1Regs.MVECT6 = (uint16_t)(&Cla1Task6);
Cla1Regs.MVECT7 = (uint16_t)(&Cla1Task7);
Cla1Regs.MVECT8 = (uint16_t)(&Cla1Task8);

//
// Enable the IACK instruction to start a task on CLA in software
// for all 8 CLA tasks. Also, globally enable all 8 tasks (or a
// subset of tasks) by writing to their respective bits in the
// MIER register
//
Cla1Regs.MCTL.bit.IACKE = 1;
Cla1Regs.MIER.all = 0x00FF;
Cla1Regs.MIFRC.all =
//
// Configure the vectors for the end-of-task interrupt for all
// 8 tasks
//
PieVectTable.CLA1_1_INT = &cla1Isr1;

//
// Enable CLA interrupts at the group and subgroup levels
//
PieCtrlRegs.PIEIER11.all = 0xFFFF;
IER |= (M_INT11 );
}

//
// cla1Isr1 - CLA1 ISR 1
//
__interrupt void cla1Isr1 ()
{
//
// Acknowledge the end-of-task interrupt for task 1
//
PieCtrlRegs.PIEACK.all = M_INT11;

//
// Uncomment to halt debugger and stop here
//
// asm(" ESTOP0");
}

Hope you can help me solve this :)