TMS320F28027F: Overhead of ADC

Hi Hideaki,

The ADC has a fixed conversion time of 13 ADCCLKS and a configurable ACQPS (sample window) that is a min of 7 ADCCLKS on the F28027. Can you expand on what you mean by overhead?

Frank,

I appreciate your response. You mean the time for ADC body. SPRUGE5F.pdf p.38 tells the same numbers.

So my point is a kind of extra time like the followings:

t1 =  The time before ADC:  Delay for PWM CmpA to kick the SOC.

t2 =  The time after ADC:  Delay for ADCINTFLG.ADCINTx to kick the CPU ISR user code.

Could you please estimate the t2 ? 

From my test it would be approx 40CLKs. Your advise would be appreciated.

Hideaki,

The delay after ADCINTFLG gets set to when the first instruction of the ISR executes "t2" takes a minimum of 14 SYSCLK cycles. The actual latency depends on various factors as shown below and highlighted in the wiki page.

You can find the details for this in the wiki page here: http://processors.wiki.ti.com/index.php/Interrupt_FAQ_for_C2000?keyMatch=interrupt&tisearch=Search-EN 

If you want to optimize your code and take advantage of that latency, you can set the ADC to interrupt after the S/H is done and not after the conversion. This will save you 13 ADCCLK cycles so by the time the ISR starts executing the first instruction, the conversion is already done and the results latched.