TMS320F28069: CPU load for Non-isolated Buck converter, 4-phase, 200kHz

Taking a 'worst case' scenario in which all the processing is done on the CPU in four separate ISRs.  Based on the C macro benchmarks in the DP library you should expect about this for each ISR:

ADC single channel read = 5 cycles

2P2Z controller = 36 Cycles

PWM driver = 10 cycles

Total for 1 loop = 51 cycles

Allowing a generous 40 cycles for context protection and some background processing, let's say 90 cycles per loop.  This device runs at 90 MHz, so four 200 kHz loops have 112 cycles available and you are within budget, although the CPU is 80% loaded.

The situation can be improved if you run a single ISR for all four loops: in that case the loading would be reduced to 100*(51*4 + 40)/450 = 54.2%.

It's better still if you exploit the CLA to handle one or more of the loops.  In principle the entire control processing could be off-loaded to the CLA, leaving the main CPU free for other tasks.

From a control perspective, this is comfortably within reach of F28069.

Regards,

Richard

You are very welcome.

I took these numbers from the digital power library documentation in controlSUITE. If you have installed that at the default location, the document (DPlib.pdf) is at:
C:\ti\controlSUITE\libs\app_libs\digital_power\f2806x_v3.5\Doc

The cycle count benchmarks are on pages 16 & 17. I could not find cycle benchmakrs in the newer SDK documentation, for some reason, but anyway these numbers give us an approximate idea.  Glad it helps.

Regards,

Richard