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TMS320F28075: Spurious SDFM output with Manchester Encoded AMC13032510 chip

Part Number: TMS320F28075
Other Parts Discussed in Thread: AMC1303E2510, AMC1306M25

Hi,

I'm using Filters1, 2 and 3 of the TMS320F28075 SDFM1 to read the Manchester Encoded output from 3 separate AMC1303E2510 chips. The AMC1303E2510 has it's own internally generated 10MHz CLK, therefore I'm using CMPC and CMPD of ePWM11 to synchronise filters1, 2 and 3 of SDFM1. After the result from each Filter is read, it is re-scaled to the DAC range (0-4095) and the 3 filter outputs are output on the 3 DACs.  I've attached the main .c file of the project below.

The problem I have is that the output from the SDFM module is wrong sometimes. In the oscilloscope shot below:

- CH1 (yellow) is a +/-10V input (via resistor divider) to the AMC1303 chip for Filter 1. +/-10V produces +/-250mV at the AMC1303 input.

- CH2 (pink) is the DAC output for Filter 1 (note that it is passed through an external op-amp buffer to increase it's amplitude).

You can see in the zoom in of CH2 that the DAC output is wrong for approx. 40us (in the code the SDFM sampling period is approx. 20us so this corresponds to 2 incorrect values from the SDFM module). I have also verified that the problem is not with the conversion to the DAC (i.e. the raw data read from the SDDATA register for filter 1 is incorrect).

The ISR routine, epwm1_isr, is triggered when ePWM1 counter is 0. It is configured in UP COUNT mode. The PWM period is set to 4 times the SDFM sampling period. This is because after a PWM sync, the first two SDFM output values are incorrect (with a SINC3 filter). ePWM11 is setup the same as ePWM1 and is synced to the ePWM1 counter by the synchronisation pulse input from ePWM1 fed through ePWM10.

ePWM11.CMPC and CMPD are set to SDFM_RESET_CMP_VALUE. SDFM_RESET_CMP_VALUE is set so that it occurs Latency of data filter + 5 SD clock cycles before the PWM counter resets to 0. Therefore after the CMPC/CMPD PWM sync there should be time for 3 SDFM output values before the ISR triggers. Therefore I'm confident that the problem is not because I am reading one of the 2 incorrect samples after a PWMSYNC event.

In the ISR the ACK and the Modulator failure flags for filters 1, 2 and 3 are checked. If any of the ACK flags are NOT set or if any of the modulator failure flags are set, then the routine pauses (using ESTOP0). However this never happens, even when there is an incorrect value.

Finally, I have seen in the datasheet and other threads that the delta-sigma chip (AMC1303E2510 in this case) CLK period must be between 8*T_SYSCLK - 20*T_SYSCLK. In my code I am using the line

InitSysPll(INT_OSC2,IMULT_10,FMULT_0,PLLCLK_BY_1);

to set the MCU CLK frequency to 100MHz. Therefore T_SYSCLK = 10ns. So the delta-sigma CLK period must be between 80ns - 200ns. For a 10MHz delta-sigma CLK, the period is 100ns so that should be fine.

Do you see anything wrong with the setup I have described? Have you seen this kind of behaviour before?

Many thanks,

Fearghal

8322.sdfm_pwm_sync_cpu_cpu01.c
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//###########################################################################
//
// FILE: sdfm_pwm_sync_cpu_cpu01.c
//
// TITLE: SDFM PWM sync Example for F2807x.
//
//! \addtogroup cpu01_example_list
//! <h1> SDFM PWM Sync </h1>
//!
//! In this example, SDFM filter data is read by CPU in SDFM ISR routine. The
//! SDFM configuration is shown below:
//! - SDFM1 is used in this example
//! - MODE2 Input control mode selected
//! - Comparator settings
//! - Sinc3 filter selected
//! - OSR = 32
//! - HLT = 0x7FFF (Higher threshold setting)
//! - LLT = 0x0000(Lower threshold setting)
//! - Data filter settings
//! - 3 filter modules enabled
//! - Sinc3 filter selected
//! - OSR = 50
//! - All the 3 filters are synchronized by using PWMSYNC
//! - Filter output represented in 16 bit format
//! - In order to convert 25 bit Data filter
//! into 16 bit format user needs to right shift by 2 bits for
//! Sinc3 filter with OSR = 50
//! - Interrupt module settings for SDFM filter
//! - All the 4 higher threshold comparator interrupts disabled
//! - All the 4 lower threshold comparator interrupts disabled
//! - All the 4 modulator failure interrupts disabled
//! - All the 4 filters will NOT generate an interrupt when a new filter data
//! is available
//! - The interrupt is controlled by ePWM1
//!
//
//###########################################################################
// $TI Release: F2807x Support Library v3.05.00.00 $
// $Release Date: Tue Jun 26 03:19:11 CDT 2018 $
// $Copyright:
// Copyright (C) 2014-2018 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • Fearghal,

    Did you try disabling PWM sync feature and check whether you still see the problem?

    Regards,
    Manoj
  • Hi Manoj,

    Yes I tried disabling the PWM sync feature but the problem persists.

    I have started a related question in the Data Converters Forum. As I explained there, when I reduced the input to +/-9V (+/-225mV at the AMC1303E2510 input) the problem went away, so I'm wondering if entering the non-linear input range of the AMC1303E2510 could be causing the problem.

    e2e.ti.com/.../791462

    Thanks,

    Fearghal
  • Hi Manoj,

    Since my last post the problem has reappeared again. The spurious results are there even when the input is +/5Vpp (+/-125mV at the AMC1303E2510 input). Therefore my attention is back on the MCU SDFM again.

    Do you have any ideas?

    Thanks,

    Fearghal
  • Fearghal,

    Since you are saying you are seeing this problem even if PWM sync is disabled, I don't think it is SDFM related.

    Also, I don't understand what you mean by "input is +/5Vpp (+/-125mV)"

    Regards,
    Manoj
  • Is this issue resolved? What was the resolution?
  • Hi Manoj,

    No we haven't resolved it. For now we have switched to the uncoded CLK'd version of the delta-sigma chip (AMC1306M25) and it is working fine.

    However I'm still hoping to figure out what's going on here so we can use the Manchester version on future projects. But unfortunately I can't find the time to investigate it further right now so I'll mark this thread as resolved for now and open a related question in the future.

    In answer to your last question, by "input is +/5Vpp (+/-125mV)" I mean the voltage input at the terminals of the AMC1303E2510 is +/-125mV. This is well within the linear input range of that chip (the linear input range is +/-250mV) therefore I don't think the problem is with the AMC1303E2510.

    Thanks,

    Fearghal