CCS/TMS320F280049C: click restart button jump to 0x3fbd92 by using XDS100V2 with <TMS320F280049C.ccxml>target file

Gavin,

The reset process should be the same regardless of the debugger selected. What error message do you observe in the console window? Typically, one will just need to switch the debugger in the target configuration file and functionality should remain the same.

Regards,

Ozino

Hi Ozino,

just imported C2000Ware sample "adc_ex1_soc_epwm", the debugger used XDS100V2 and check again. it can use "restart" button normally.

maybe there is some wrong with my project setting. 

below is the screenshot of my project after I clicked "reset" button. and I also attach the .cmd file my project using.

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN            : origin = 0x000000, length = 0x000002
   RAMM0            : origin = 0x0000F3, length = 0x00030D

   RAMLS0           : origin = 0x008000, length = 0x000800
   RAMLS1           : origin = 0x008800, length = 0x000800
   RAMGS0_2         : origin = 0x00C000, length = 0x006000
   RESET            : origin = 0x3FFFC0, length = 0x000002


PAGE 1 :

   BOOT_RSVD       : origin = 0x000002, length = 0x0000F1     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMLS2           : origin = 0x009000, length = 0x000800
   RAMLS3           : origin = 0x009800, length = 0x000800
   RAMLS4           : origin = 0x00A000, length = 0x000800
   RAMLS5           : origin = 0x00A800, length = 0x000800
   RAMLS6           : origin = 0x00B000, length = 0x000800
   RAMLS7           : origin = 0x00B800, length = 0x000800

//   RAMGS1           : origin = 0x00E000, length = 0x002000
//   RAMGS2           : origin = 0x010000, length = 0x002000
   RAMGS3           : origin = 0x012000, length = 0x001FF8
//   RAMGS3_RSVD      : origin = 0x013FF8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   CLA1_MSGRAMLOW   : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH  : origin = 0x001500, length = 0x000080
}

/*You can arrange the .text, .cinit, .const, .pinit, .switch and .econst to FLASH when RAM is filled up.*/
SECTIONS
{
   codestart        : > BEGIN,     PAGE = 0
   .TI.ramfunc      : > RAMGS0_2,   PAGE = 0
   .text            : > RAMGS0_2,   PAGE = 0
   .cinit           : > RAMLS0,     PAGE = 0
   .switch          : > RAMM0,     PAGE = 0
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   .stack           : > RAMM1,     PAGE = 1

   #if defined(__TI_EABI__)
   .bss             : > RAMLS5,     PAGE = 1
   .bss:output      : > RAMLS5,     PAGE = 1
   .init_array      : > RAMM0,      PAGE = 0
   .const           : > RAMLS6,     PAGE = 1
   .data            : > RAMLS6,     PAGE = 1
   .sysmem          : > RAMLS6,     PAGE = 1
   .bss:cio         : > RAMLS5,     PAGE = 1
#else
   .pinit           : > RAMM0,      PAGE = 0
   .ebss            : >> RAMLS3 | RAMLS4,     	   PAGE = 1
   .econst          : >> RAMLS5 | RAMLS6 | RAMLS7,  PAGE = 1
   .esysmem         : > RAMLS6,     PAGE = 1
   .cio             : > RAMLS5,     PAGE = 1
#endif

   // CLA Sections
   Cla1Prog         : > RAMLS1,           PAGE = 0
   .scratchpad      : > RAMLS2,           PAGE = 1
   .bss_cla         : > RAMLS2,           PAGE = 1
   .const_cla       : > RAMLS2,           PAGE = 1
   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1
   Cla1DataRam      : > RAMLS2,           PAGE = 1
   ramgs0           : > RAMGS3,    PAGE = 1
   ramgs1           : > RAMGS3,    PAGE = 1
   cla_shared       : > RAMLS2,           PAGE = 1
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Hi Ozino,

It's running at RAM.

this issue was resolved.  None biz with debugger, there is sth  wrong with user code. 

thanks for your support.

Gavin,

Glad you figured it out. Thanks for sharing the feedback.

Regards,

Ozino