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TMS320F28375S: how to get configuration for SPI CLK Active high and latch on the falling edge

Eyal Saban1
Intellectual 855 points
Part Number: TMS320F28375S

Dear SIr, 

we are developing controller based on 28376S   and have some issue  to reach specifc SPI configuration.Our controller is the SPI Master and sends   3xSPI Word each of 12bit   with SPI Clock of 1Mhz,

the Slave clock scheme  is clocking data on the falling edge (this is how we configure as well ) and latching on the rising (SPi Master as well.).

the issue that we are seeing is when setting SPI with Clock polarity =1   (e.g. shift on falling and latch on rising )   the SPI CLK  is at high during start of fram (e.g CS is going to low) , which cause us to miss 1 bit 

what we need is the SPI Clock to start at low level during start of frame  , but latch on the rising edge  as shown below , how can it be accomplished ?

  • 0
    TI__Guru 55700 points

    Eyal,

    what we need is the SPI Clock to start at low level during start of frame  , but latch on the rising edge  as shown below , how can it be accomplished ?

    Did you miss to attach the image? I didn't see any scopeshot below?

    But, I wanted to let you know that you configure SPISTEn (chip select) as GPIO output pin, you have the flexibility to bring CS pin low much before.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Intellectual 855 points

    Hi Manjo , 

    i  am sorry , i tought that the pciture was attched  , please find below :

    i think i have manged to het to this configuration  by setting 

    1. clock polarity to 0   (e.g. IDLE is low )

    2. clock Phase to 1   (transmit one half cycle before rising edge , latch on rising edge  )   ,   assuming  CLK D.C is 50%  this is means 

         shift on falling edge / latch on rising edge    , am i correct ?

  • 0 in reply to Eyal Saban1
    TI__Guru 55700 points

    Eyal,

    When clock polarity is 0, idle is indeed low signal as shown in below figure. I believe you are trying to configure SPI in mode 1 (POL = 0, PHA = 1). In that case receving data in indeed latched on rising edge. For better diagram, please refer Figure5-73 in F2837xS DS and make sure you meet the timing requirement specified in DS.

    Regards,

    Manoj