TMS320F28379D: Code size error "Program will not fit into the available memory"

//###########################################################################
//
// FILE:    control_cpu01.c
//
// TITLE:   Inverter Control (SVPWM)
//
//!
//!
//!
//###########################################################################

//
// Included Files

#define   MATH_TYPE      FLOAT_MATH    //IQ_MATH
#include "IQmathLib.h"
#include <math.h>
#include "F28x_Project.h"
#include "settings.h"
#include "Solar_F.h"


// Function Prototypes
void InitEPwm(void);
void ConfigureADC(void);
__interrupt void epwm1_isr(void);
__interrupt void adca1_isr(void);


Uint16 usRunState;
Uint16 usFaultFlag;
Uint16 usResumePWM;

Uint16 usPwmPeriod;
Uint16 EPwm1_DB;
Uint16 EPwm2_DB;
Uint16 EPwm3_DB;
Uint16 usPhase;
Uint16 usPwm2Phase;
Uint16 usPwm3Phase;
Uint16 EPwm1_CMP;
Uint16 EPwm2_CMP;
Uint16 EPwm3_CMP;
float32 fDutyCycle;
float32 fDutyCycle1;
float32 fDutyCycle2;
float32 fDutyCycle3;
float32 fTdb;
float32 fTdb2;
float32 fTdb3;
Uint16 TestPwm;
float32 fVdcRef;
float32 fVinFlt;
float32 fVdcPeak;



float32 fUma;
float32 fUmb;
float32 fUmc;
float32 fUmz;
float32 fUmax;
float32 fUmin;
float32 fUmaxAbs;
float32 fUminAbs;
float32 fUmodA;
float32 fUmodB;
float32 fUmodC;
float32 fUmodAlpha;
float32 fUmodBeta;
Uint16 usCmpValA;
Uint16 usCmpValB;
Uint16 usCmpValC;

float32 fMI240;

// ADC values
float32 fVa;
float32 fVb;
float32 fVc;
float32 fVab;
float32 fVbc;
float32 fVca;

float32 fVpert;
float32 fVout;
float32 fVoutFlt;
float32 fIdc;
float32 fIindA;
float32 fIindB;
float32 fIindC;
float32 fIa;
float32 fIb;
float32 fIc;
float32 fIaNorm;
float32 fIbNorm;
float32 fIcNorm;
float32 fIdcFlt;
float32 fWTLpfIind;
float32 fIindAFlt;
float32 fIindBFlt;
float32 fIindCFlt;
float32 fCurrentFaultDc;
float32 fCurrentFaultA;
float32 fCurrentFaultB;
float32 fCurrentFaultC;
float32 fOver_Current;
float32 fOver_Voltage;
float32 fVoutFault;
float32 fIindFlt;
float32 fIrefMag;
float32 fIrefLimit;
float32 fIset;
float32 fSlope;

float32 fVerr;
float32 fKp2;
float32 fKi2;
float32 fInt2;

float32 fCurrentRef;
float32 fIerrA;
float32 fIerrB;
float32 fIerrC;
float32 fIntA;
float32 fIntB;
float32 fIntC;
float32 fCurrCtrlA;
float32 fCurrCtrlB;
float32 fCurrCtrlC;

float32 fIref;
float32 fIerr;
float32 fInt;
float32 fIerr;
float32 fCurrCtrl;

float32 fSineA;
float32 fSineB;
float32 fSineC;
float32 fSineAB;
float32 fSineBC;
float32 fSineCA;
float32 fThetaA;
float32 fThetaB;
float32 fThetaC;
float32 fThetaAB;
float32 fThetaBC;
float32 fThetaCA;
float32 fPhaseComp;

float32 fVaAbs;
float32 fVbAbs;
float32 fVcAbs;
float32 fVabAbs;
float32 fVbcAbs;
float32 fVcaAbs;
float32 fVdc;
float32 fScale1;
float32 fScale2;
float32 fScale3;
float32 fScale4;
float32 fOffset1;
float32 fOffset2;
float32 fOffset3;
float32 fOffset4;
float32 fgainVo;
float32 foffsetVo;
float32 fgainIdc;
float32 foffsetIdc;
float32 fgainIindC;
float32 foffsetIindC;
float32 fgainIindB;
float32 foffsetIindB;
float32 fgainIindA;
float32 foffsetIindA;
float32 fIaOffset;
float32 fIaOffset2;
float32 fIagain1;
float32 fIagain2;
float32 fIbOffset;
float32 fIbOffset2;
float32 fIbgain1;
float32 fIbgain2;
float32 fIcOffset;
float32 fIcOffset2;
float32 fIcgain1;
float32 fIcgain2;

float32 fNormalize;

float32 fDBCompThres;
float32 fDBCompCoeff;
float32 fDBCompA;
float32 fDBCompB;
float32 fDBCompC;

float32 fVmagSq;
float32 fVmag;
float32 fVmagFlt;
float32 fVmagFltWt;

float32 fIin_ref1;
float32 fIin_ref2;
float32 fIslope;

/*float32 VdTesting;
float32 VqTesting;*/
float32 Feedback_vd;
float32 Feedback_vq;
float32 fid_CurrentRef;
float32 fid_ref;
float32 fIerr1;
float32 fInt1;
float32 fCurrCtrl1;
float32 fiq_CurrentRef;
float32 fiq_ref;
float32 fIerr2;
float32 fInt2;
float32 fCurrCtrl2;
float32 fKp;
float32 fKi;

float32 Min;
float32 Max;
float32 A;
float32 B;
float32 C;
float32 Vlink_ref;
/*
float32 un;
float32 un_1;
float32 un_2;
float32 en;
float32 en_1;
float32 en_2;
float32 b2;
float32 b1;
float32 b0;
float32 a2;
float32 a1;
*/

// Variables for viewing signals in CCS graph
#define RESULTS_BUFFER_SIZE 128
int16 Adc1[RESULTS_BUFFER_SIZE];
int16 Adc2[RESULTS_BUFFER_SIZE];
int16 Adc3[RESULTS_BUFFER_SIZE];
int16 Adc4[RESULTS_BUFFER_SIZE];
Uint16 resultsIndex;
Uint16 saveIndex;
volatile Uint16 bufferFull;
Uint16 usStartSaveData;
Uint16 samplePace;

// ****************************************************************************
// Variables for MACROS
// ****************************************************************************
float32 T = 1.0/PWM_FREQUENCY;    // Samping period (sec), see parameter.h

_iq     VdTesting = _IQ(0.93),           // Vd reference (pu)
    VqTesting = _IQ(0.0),          // Vq reference (pu)
   IdRef     = _IQ(0.0),           // Id reference (pu)
    IqRef     = _IQ(0.0),           // Iq reference (pu)
    SpeedRef  = _IQ(1.0),           // For Closed Loop tests
    lsw1Speed = _IQ(0.02);          // initial force rotation speed in search of QEP index pulse

// Instance a few transform objects (ICLARKE is added into SVGEN module)
CLARKE clarke1 = CLARKE_DEFAULTS;
ICLARKE_M iclarke1 = ICLARKE_M_DEFAULTS;
PARK_M park1 = PARK_M_DEFAULTS;
IPARK_M ipark1 = IPARK_M_DEFAULTS;
PI_CONTROLLER   pi_id   = PI_CONTROLLER_DEFAULTS;
PI_CONTROLLER   pi_iq   = PI_CONTROLLER_DEFAULTS;
//PHASEVOLTAGE volt1 = PHASEVOLTAGE_DEFAULTS;
// Instance a Space Vector PWM modulator. This modulator generates a, b and c
// phases based on the d and q stationery reference frame inputs

SVGENDPWM_240 svgen1 = SVGENDPWM_240_DEFAULTS;
//SVGEN svgen1 = SVGEN_DEFAULTS;

// Instance a ramp controller to smoothly ramp the frequency
RMPCNTL rc1 = RMPCNTL_DEFAULTS;

//  Instance a ramp(sawtooth) generator to simulate an Angle

RAMPGEN rg1 = RAMPGEN_DEFAULTS;
// ****************************************************************************
// Variables for Datalog module
// ****************************************************************************
//float DBUFF_4CH1[100],
//      DBUFF_4CH2[100],
//      DBUFF_4CH3[50],
//      DBUFF_4CH4[50],
//      DlogCh1,
//      DlogCh2,
//      DlogCh3,
//      DlogCh4;


void Shutdown(void);

//
// Main
//
void main(void)

{

    InitSysCtrl();

    CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM7 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM8 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM9 = 1;

    InitEPwm1Gpio();
    InitEPwm2Gpio();
    InitEPwm3Gpio();

    InitEPwm7Gpio();
    InitEPwm8Gpio();
    InitEPwm9Gpio();


        EALLOW;
        GpioCtrlRegs.GPAMUX2.bit.GPIO20  = 0; // GPIO
        GpioCtrlRegs.GPADIR.bit.GPIO20  = 1;   // output
        EDIS;


    DINT;

    InitPieCtrl();

    IER = 0x0000;
    IFR = 0x0000;

    InitPieVectTable();

//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.EPWM1_INT = &epwm1_isr;
//  PieCtrlRegs.PIEIER3.bit.INTx7 = 1;
    PieVectTable.ADCA1_INT = &adca1_isr; //function for ADCA interrupt 1
    EDIS;   // This is needed to disable write to EALLOW protected registers

// Configure the ADC and power it up
// Setup the ADC for ePWM triggered conversions
// ************ SHOULD BE DONE BEFORE PWM CONFIG **************
    ConfigureADC();
//
// Step 4. Initialize the Device Peripherals:
//
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
    EDIS;

    InitEPwm();

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
    EDIS;



//
// Step 5. User specific code
// Initialize variables
    // Initialize variables
        usRunState = 0;
        usResumePWM = 0;
        fOver_Current = 40.0;
        fOver_Voltage = 950.0;

        fid_ref = 5;
        fiq_ref = 0;
        fKp = 0.06;//0.1;
        fKi = 20; //10;

/*        en_2 = 0;
        en_1 = 0;
        un_2 = 0;
        un_1 = 0;
        en = 0;
        un = 0;
        b2 = -0.002930185534789;
        b1 = 0.000503233879362;
        b0 = 0.003433419414151;
        a2 = 0.110340072507284;
        a1 = 0.889659927492716;*/


    fVinFlt = 50;
    fVdcPeak = 100;
//    fVdcRef = 100;
    fMI240 = 1.0;
    fVmagFltWt = TWO_PI * 5000 * SAMPLING_PERIOD; // 20 kHz LPF
    fPhaseComp = 0.0;

    fDBCompCoeff = 1.0;
    fDBCompThres = 5.0;
    fDBCompA = 1.0;
    fDBCompB = 1.0;
    fDBCompC = 1.0;

/*
    // Init PI module for ID loop
   pi_id.Kp   = _IQ(0.2);//_IQ(3.0);
   pi_id.Ki   = _IQ(10.0);//_IQ(T/0.04);//0.0075);
   pi_id.Umax = _IQ(0.5);
   pi_id.Umin = _IQ(-0.5);

   // Init PI module for IQ loop
   pi_iq.Kp   = _IQ(0.2);//_IQ(4.0);
   pi_iq.Ki   = _IQ(10.0);//_IQ(T/0.04);//_IQ(0.015);
   pi_iq.Umax = _IQ(0.8);
   pi_iq.Umin = _IQ(-0.8);*/

    rg1.StepAngleMax = _IQ(GRID_FREQ * SAMPLING_PERIOD);
//    SPLL_3ph_SRF_F_init(GRID_FREQ, SAMPLING_PERIOD, &spll1);
//    Kp = 166.6;
//    Ki = 27755.55;
//    T = 1/10e3;
//    B0 = (2*Kp + Ki*T)/2
//    B1 = -(2*Kp - Ki*T)/2


    fNormalize = 0.1;




    // ****************************************************
    // Initialize DATALOG module
    // ****************************************************
//    DLOG_4CH_F_init(&dlog_4ch1);
//    dlog_4ch1.input_ptr1 = &DlogCh1;    //data value
//    dlog_4ch1.input_ptr2 = &DlogCh2;
//    dlog_4ch1.input_ptr3 = &DlogCh3;
//    dlog_4ch1.input_ptr4 = &DlogCh4;
//    dlog_4ch1.output_ptr1 = &DBUFF_4CH1[0];
//    dlog_4ch1.output_ptr2 = &DBUFF_4CH2[0];
//    dlog_4ch1.output_ptr3 = &DBUFF_4CH3[0];
//    dlog_4ch1.output_ptr4 = &DBUFF_4CH4[0];
//    dlog_4ch1.size = 200;
//    dlog_4ch1.pre_scalar = 5;
//    dlog_4ch1.trig_value = 0.01;
//    dlog_4ch1.status = 2;

    for(resultsIndex = 0; resultsIndex < RESULTS_BUFFER_SIZE; resultsIndex++)
    {
        Adc1[resultsIndex] = 0;
        Adc2[resultsIndex] = 0;
        Adc3[resultsIndex] = 0;
        Adc4[resultsIndex] = 0;
    }

    resultsIndex = 0;
    saveIndex = 0;
    bufferFull = 0;
    samplePace = 4; // Rounding( F_sample / F_fundamental / BufferSize )
    usStartSaveData = 0;

  fgainVo = 345.423;
  foffsetVo = 0;
  fgainIdc = 103.1;
  fgainIindC = 108.7;
  fgainIindB = 142.5;
  fgainIindA = 142.5;
  foffsetIdc = 1.507;
  foffsetIindC = 1.507;
  foffsetIindB = 1.506;
  foffsetIindA = 1.506;

  fIaOffset = 2.222;
  fIagain1 = -2;
  fIagain2 = 15.5;
  fIaOffset2 = -0.0118;

  fIbOffset = 2.222;
  fIbgain1 = -2;
  fIbgain2 = 15.5;
  fIbOffset2 = 0;

  fIcOffset = 2.222;
  fIcgain1 = -2;
  fIcgain2 = 15.5;
  fIcOffset2 = -0.0118;


//
// Enable CPU INT3 which is connected to EPWM1-3 INT:
//
    // IER |= M_INT3;
    IER |= M_INT1; // for ADC isr
    EINT;  // Enable Global interrupt INTM
    ERTM;  // Enable Global realtime interrupt DBGM

//
// Enable PIE interrupt
//
    // PieCtrlRegs.PIEIER3.bit.INTx1 = 1; // PWM
    PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // ADC isr

   // conv_duty();

    for(;;)
    {
        asm ("          NOP");
    }
}

//
// epwm1_isr - EPWM1 ISR
//
__interrupt void epwm1_isr(void)
{
//    GpioDataRegs.GPASET.bit.GPIO8 = 1; // Pin 57

    asm ("          NOP"); asm ("          NOP");
    asm ("          NOP"); asm ("          NOP");
    asm ("          NOP"); asm ("          NOP");
    asm ("          NOP"); asm ("          NOP");
    asm ("          NOP"); asm ("          NOP");

//    EPwm2Regs.TBPHS.bit.TBPHS = usPwm2Phase;
//    EPwm3Regs.TBPHS.bit.TBPHS = usPwm3Phase;
//    EPwm1Regs.TBPRD = usPwmPeriod;
//    EPwm2Regs.TBPRD = usPwmPeriod;
//    EPwm3Regs.TBPRD = usPwmPeriod;


//    GpioDataRegs.GPACLEAR.bit.GPIO8 = 1;

    // Clear INT flag for this timer
    EPwm1Regs.ETCLR.bit.INT = 1;
    // Acknowledge this interrupt to receive more interrupts from group 3
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

//
// adca1_isr - Read ADC Buffer in ISR
//
__interrupt void adca1_isr(void)
{
     GpioDataRegs.GPASET.bit.GPIO20 = 1;

    //**********************************************
    // Get ADC Results
    //**********************************************
 //   fVab    = fScale2 * (((float32)AdcaResultRegs.ADCRESULT0) * 0.0007326007326) + fOffset2;
//    fVa    = fScale2 * (((float32)AdcaResultRegs.ADCRESULT6) * 0.0007326007326) + fOffset2;
//    fVb    = fScale3 * (((float32)AdcaResultRegs.ADCRESULT7) * 0.0007326007326) + fOffset3;
//    fVc    = fScale4 * (((float32)AdcaResultRegs.ADCRESULT3) * 0.0007326007326 + fOffset4);
//    fVc = 0.0 - fVa - fVb;

//  New PCB
   fVout  = ((float32)AdcaResultRegs.ADCRESULT0 * 0.0007326007326) * fgainVo + foffsetVo;
   fIdc   = ((float32)AdcaResultRegs.ADCRESULT1 * 0.0007326007326 - foffsetIdc) * (-1*fgainIdc); //108.7 1.504
   fIindC = ((float32)AdcaResultRegs.ADCRESULT2 * 0.0007326007326 - foffsetIindC) * fgainIindC; //95.54
   fIindB = ((float32)AdcaResultRegs.ADCRESULT3 * 0.0007326007326 - foffsetIindB) * fgainIindB; //108.7
   fIindA = ((float32)AdcaResultRegs.ADCRESULT4 * 0.0007326007326 - foffsetIindA) * fgainIindA; //108.7
   fVpert = ((float32)AdcaResultRegs.ADCRESULT6 * 0.0007326007326);  //ADCIN14 goes in Result6
//        fVpert = (1.905-(float32)AdcaResultRegs.ADCRESULT6 * 0.0007326007326) * 3.703703;  //ADCIN14 goes in Result6

   fIa = ((((float32)AdcbResultRegs.ADCRESULT0 * 0.0007326007326 - fIaOffset ) - fIaOffset2) * fIagain1) * fIagain2;
   fIb = ((((float32)AdcbResultRegs.ADCRESULT1 * 0.0007326007326 - fIbOffset ) - fIbOffset2) * fIbgain1) * fIbgain2;
   fIc = ((((float32)AdcbResultRegs.ADCRESULT2 * 0.0007326007326 - fIcOffset ) - fIcOffset2) * fIcgain1) * fIcgain2;

//   fIc = (((float32)AdcbResultRegs.ADCRESULT2 * 0.0007326007326 - fIcOffset ) * fIcgain1) * fIcgain2;

 EMATH_OneOrderLpf(fIa, fIaNorm, fVmagFltWt);
 EMATH_OneOrderLpf(fIb, fIbNorm, fVmagFltWt);
 EMATH_OneOrderLpf(fIc, fIcNorm, fVmagFltWt);



    //For CSVPWM & DPWM1
 //   For open loop testing

    // ------------------------------------------------------------------------------
    //  Connect inputs of the RMP module and call the ramp control macro
    // ------------------------------------------------------------------------------
    rc1.TargetValue = SpeedRef;
    RC_MACRO(rc1)

    // ------------------------------------------------------------------------------
    //  Connect inputs of the RAMP GEN module and call the ramp generator macro
    // ------------------------------------------------------------------------------
    rg1.Freq = rc1.SetpointValue;
    RG_MACRO(rg1)


    // Calculate Duty for Boost converter
    fThetaA = rg1.Out * TWO_PI;
    fThetaB = fThetaA + FOUR_PI_DIV3;
    if( fThetaB > TWO_PI ) { fThetaB = fThetaB - TWO_PI; }
    fThetaC = fThetaA + TWO_PI_DIV3;
    if( fThetaC > TWO_PI ) { fThetaC = fThetaC - TWO_PI; }

    fSineA = sin(fThetaA);
    fSineB = sin(fThetaB);
    fSineC = sin(fThetaC);
    fSineAB = (fSineA - fSineB);
    fSineBC = (fSineB - fSineC);
    fSineCA = (fSineC - fSineA);

    fVabAbs = ABS(fSineAB);
    fVbcAbs = ABS(fSineBC);
    fVcaAbs = ABS(fSineCA);
    fVdc = MAX_THREE(fVabAbs, fVbcAbs, fVcaAbs);
    UP_DOWN_LIMIT(fVdc, 1.733, 0.1);
    fMI240 = 1.7320508 / fVdc;
    UP_DOWN_LIMIT(fMI240, 1.154, 0.5);



    //Connecting phase currents with Clark Macro

   clarke1.As = fIa; //fIaNorm; // Phase A curr.
   clarke1.Bs = fIb; //fIbNorm; // Phase B curr.
   CLARKE_MACRO(clarke1)

   // ------------------------------------------------------------------------------
   //  Connect inputs of the PARK module and call the park trans. macro
   // ------------------------------------------------------------------------------
    park1.Alpha  = clarke1.Alpha;
    park1.Beta   = clarke1.Beta;
    park1.Angle  = rg1.Out;
    park1.Sine   = __sinpuf32(park1.Angle);
    park1.Cosine = __cospuf32(park1.Angle);
    PARK_M_MACRO(park1)

    //TI - PI Control
    pi_id.Ref = fid_ref;
    pi_id.Fbk = park1.Ds;
    PI_MACRO(pi_id);

    pi_iq.Ref = fiq_ref;
    pi_iq.Fbk = park1.Qs;
    PI_MACRO(pi_iq);

    //Close Loop Control of Inverter Side
    fid_CurrentRef  = fid_ref;
    fIerr1 = fid_CurrentRef - park1.Ds;
    fInt1 += fIerr1 * fKi * CONTROL_PERIOD;
    UP_DOWN_LIMIT(fInt1, 1, -1);
    fCurrCtrl1 = fKp * fIerr1 + fInt1;
    UP_DOWN_LIMIT(fCurrCtrl1, 1.0, 0.1);
    Feedback_vd  = fCurrCtrl1;

    fiq_CurrentRef  = fiq_ref;
    fIerr2 = fiq_CurrentRef - park1.Qs;
    fInt2 += fIerr2 * fKi * CONTROL_PERIOD;
    UP_DOWN_LIMIT(fInt2, 1, -1);
    fCurrCtrl2 = fKp * fIerr2 + fInt2;
    UP_DOWN_LIMIT(fCurrCtrl2, 0.0, 0.0);
    Feedback_vq  = fCurrCtrl2;

    ipark1.Ds =  Feedback_vd; //pi_id.Out;
    ipark1.Qs =  Feedback_vq;  //pi_iq.Out;
    ipark1.SineA=sin(fThetaA);
    ipark1.SineB=sin(fThetaB);
    IPARK_M_MACRO(ipark1)

    iclarke1.Valpha = ipark1.Alpha;
    iclarke1.Vbeta = ipark1.Beta;
    ICLARKE_M_MACRO(iclarke1)

    A = SQRT_THREE_RECIP * iclarke1.As;
    B = SQRT_THREE_RECIP * iclarke1.Bs;
    C = SQRT_THREE_RECIP * iclarke1.Cs;
    Max = MAX_THREE(A,B,C);
    Min = MIN_THREE(A,B,C);
    Vlink_ref = (Max - Min) * fVdcPeak;
    UP_DOWN_LIMIT(Vlink_ref, 1000.0, 50.0);

    // ------------------------------------------------------------------------------
//      Connect inputs of the SVGEN module and call the space-vector gen. macro
//     ------------------------------------------------------------------------------
//    fUmodAlpha = fSineA;
//    fUmodBeta  = (fSineA + 2.0 * fSineB) * 0.57735026918963;
//    svgen1.Ualpha = fUmodAlpha * Feedback_vd;
//    svgen1.Ubeta  = fUmodBeta * Feedback_vd;


    svgen1.Ualpha = ipark1.Alpha;
    svgen1.Ubeta  = ipark1.Beta;
    /*
//    For CSVPWM
    svgen1.Ualpha = ipark1.Alpha;
    svgen1.Ubeta  = ipark1.Beta;
*/

/*

    // DPWM 1 (clamp at peak)  //While using DPWM1, use Vdtesting = 0.93*1.15
    fUma = ipark1.Alpha;
    fUmb = 0.5*( 1.732050807 * ipark1.Beta - ipark1.Alpha);
    fUmc = 0.5*(-1.732050807 * ipark1.Beta - ipark1.Alpha);
    fUmax = MAX_THREE(fUma, fUmb, fUmc);
    fUmin = MIN_THREE(fUma, fUmb, fUmc);
    fUmaxAbs = ABS(fUmax);
    fUminAbs = ABS(fUmin);
    if( fUmaxAbs > fUminAbs )
    {
        fUmz = 1.0 - fUmax;
    }
    else
    {
        fUmz = -1.0 - fUmin;
    }
    fUmodA = fUma + fUmz;
    fUmodB = fUmb + fUmz;
    fUmodC = fUmc + fUmz;
*/

    SVGENDPWM_240_MACRO(svgen1)
//    SVGENDQ_MACRO(svgen1)            //  For CSVPWM
    //SVGENDPWM_MACRO(svgen1)
    // ------------------------------------------------------------------------------
    //   Computed Duty and Write to CMPA register
    //------------------------------------------------------------------------------
//    if(TestPwm == 1)
//    {
//        EPwm11Regs.CMPA.bit.CMPA = INV_PWM_TBPRD * fDutyCycle;
//        EPwm12Regs.CMPA.bit.CMPA = INV_PWM_TBPRD * fDutyCycle;
//        EPwm9Regs.CMPA.bit.CMPA = INV_PWM_TBPRD * fDutyCycle;
//
//    }

//

/* //   For CSVPWM
    fUmodA = svgen1.Ta;
    fUmodB = svgen1.Tb;
    fUmodC = svgen1.Tc;*/

//    240CPWM
    fUmodA = -svgen1.Ta;
    fUmodB = -svgen1.Tb;
    fUmodC = -svgen1.Tc;

//    if( fVaAbs > fDBCompThres )
//    {
//        fDBCompA = fDBCompCoeff;
//    }
//
//    if( fVbAbs > fDBCompThres )
//    {
//        fDBCompB = fDBCompCoeff;
//    }
//
//    if( fVcAbs > fDBCompThres )
//    {
//        fDBCompC = fDBCompCoeff;
//    }
//
//    fUmodA = fUmodA * fDBCompA;
//    fUmodB = fUmodB * fDBCompB;
//    fUmodC = fUmodC * fDBCompC;

    usCmpValA = (INV_PWM_HALF_TBPRD * fUmodA) + INV_PWM_HALF_TBPRD;
    usCmpValB = (INV_PWM_HALF_TBPRD * fUmodB) + INV_PWM_HALF_TBPRD;
    usCmpValC = (INV_PWM_HALF_TBPRD * fUmodC) + INV_PWM_HALF_TBPRD;

    UP_DOWN_LIMIT(usCmpValA, INV_PWM_TBPRD, 0);
    UP_DOWN_LIMIT(usCmpValB, INV_PWM_TBPRD, 0);
    UP_DOWN_LIMIT(usCmpValC, INV_PWM_TBPRD, 0);

//    EPwm11Regs.CMPA.bit.CMPA = usCmpValA; //phase A
//    EPwm12Regs.CMPA.bit.CMPA = usCmpValB; //phase B
    EPwm7Regs.CMPA.bit.CMPA  = usCmpValA; //phase A
    EPwm8Regs.CMPA.bit.CMPA  = usCmpValB; //phase B
    EPwm9Regs.CMPA.bit.CMPA  = usCmpValC; //phase C

    if( (ACTIVE == usRunState) && (NORMAL == usFaultFlag) )
        {
            if( usResumePWM )
            {
                // only need to change here for enabling/disabling phases
                EALLOW;
                GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Phase A Main
                GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;
                GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Phase B Main
                GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;
                GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Phase C Main
                GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1;
                GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Phase C Aux
                GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1;
                GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Phase B Aux
                GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1;
                GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Phase A Aux
                GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1;
                EDIS;
                usResumePWM = 0;
            }

            if( (fOver_Current <= ABS(fIdc) ) ||
                (fOver_Current <= ABS(fIindA)) ||
                (fOver_Current <= ABS(fIindB)) ||
                (fOver_Current <= ABS(fIindC)) )
            {
                Shutdown();
                fCurrentFaultDc = fIdc;
                fCurrentFaultA  = fIindA;
                fCurrentFaultB  = fIindB;
                fCurrentFaultC  = fIindC;
                usFaultFlag = OVER_CURRENT;
            }

            if( fOver_Voltage <= ABS(fVout) )
            {
                Shutdown();
                fVoutFault = fVout;
                usFaultFlag = OVER_VOLTAGE;
            }


// For CSVPWM
//           fDutyCycle = fVinFlt / fVdcRef; // for top switch
       //  fDutyCycle = fDutyCycle1 + fVpert;
// For 240CPWM
//            fVdcRef = fVdc * SQRT_THREE_RECIP * fVdcPeak;
//            UP_DOWN_LIMIT(fVdcRef, 1000.0, 50.0);

            fDutyCycle = fVinFlt / Vlink_ref; // for top switch

           UP_DOWN_LIMIT(fDutyCycle, 0.8, 0.3);
           fDutyCycle2 = fDutyCycle;
           fDutyCycle3 = fDutyCycle;

            // For Ramp Change in Reference
          /*  if (fIin_ref2 > fIin_ref1)
            {
                fIin_ref1 += fIslope;
            }
            else if (fIin_ref2 < fIin_ref1)
            {
                fIin_ref1 -= fIslope;
            }
            else
            {
                fIin_ref1 = fIin_ref2;
            }

                fCurrentRef  = fIin_ref1;  //For Ramp*/

//Close Loop Control for Iin
           /*        // PI CONTROL Current Control
                    fCurrentRef  = fIref;

                    fIerr = fCurrentRef - fIdc;
                   fInt += fIerr * fKi * CONTROL_PERIOD;
                   UP_DOWN_LIMIT(fInt, 0.8, -0.8);
                   fCurrCtrl = fKp * fIerr + fInt;
                   UP_DOWN_LIMIT(fCurrCtrl, 0.8, 0.2);
                   fDutyCycle  = 1.0 - fCurrCtrl;*/
//Function call to k factor control
 /*           fCurrentRef  = fIref;
            fIerr = fCurrentRef - fIdc;

            fCurrCtrl = Iin_control(fIerr);
            UP_DOWN_LIMIT(fCurrCtrl, 0.8, 0.2);
            fDutyCycle  = 1.0 - fCurrCtrl;
*/
           UP_DOWN_LIMIT(fDutyCycle, 0.8, 0.2);
           fDutyCycle2 = fDutyCycle;
           fDutyCycle3 = fDutyCycle;

           EPwm1_CMP = (Uint16)(fDutyCycle *  (0.5 * (float32)DC_DC_CONTROL_TBPRD));
           EPwm2_CMP = (Uint16)(fDutyCycle2 * (0.5 * (float32)DC_DC_CONTROL_TBPRD));
           EPwm3_CMP = (Uint16)(fDutyCycle3 * (0.5 * (float32)DC_DC_CONTROL_TBPRD));

           EPwm1Regs.CMPA.bit.CMPA = EPwm1_CMP; // Phase A Main
           EPwm2Regs.CMPA.bit.CMPA = EPwm2_CMP; // Phase B Main
           EPwm3Regs.CMPA.bit.CMPA = EPwm3_CMP; // Phase C Main

        }
           else
           {
               Shutdown();
           }

//    EPwm1_DB = (Uint16)(fTdb * 0.1);
//    EPwm11Regs.DBFED.bit.DBFED = EPwm1_DB;
//    EPwm12Regs.DBFED.bit.DBFED = EPwm1_DB;
//    EPwm9Regs.DBFED.bit.DBFED = EPwm1_DB;

//    //  Connect inputs of the DATALOG module
//    DlogCh1 = svgen1.Ta;
//    DlogCh2 = svgen1.Tb;
//    DlogCh3 = svgen1.Tc;
//    DlogCh4 = DlogCh2 - DlogCh3;
//    // ------------------------------------------------------------------------------
//    //    Call the DATALOG update function.
//    // ------------------------------------------------------------------------------
//    DLOG_4CH_F_FUNC(&dlog_4ch1);

    //**********************************************
    // View data in CCS graph
    //**********************************************
    if( usStartSaveData == 1 )
    {
        saveIndex++;
        if( (bufferFull == 0) && (samplePace <= saveIndex) )
        {
            Adc1[resultsIndex] = Vlink_ref *10.0;
            Adc2[resultsIndex] = Vlink_ref *10.0;
            Adc3[resultsIndex] = park1.Qs *100.0;
            Adc4[resultsIndex] = Vlink_ref *10.0;

//            Adc1[resultsIndex] = ipark1.Alpha *100.0;
//            Adc2[resultsIndex] = ipark1.Beta *100.0;
//            Adc3[resultsIndex] = svgen1.Ualpha *100.0;
//            Adc4[resultsIndex] = svgen1.Ubeta *100.0;

            resultsIndex++;
            saveIndex = 0;
        }

        if(RESULTS_BUFFER_SIZE <= resultsIndex)
        {
            resultsIndex = 0;
            bufferFull = 1;
            saveIndex = 0;
            usStartSaveData = 0;
        }
    }

     GpioDataRegs.GPACLEAR.bit.GPIO20 = 1;

    AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

//
// InitEPwm - Initialize EPWMx configuration
//
void InitEPwm()
{
    fTdb  = 250.0; // ns
       fTdb2 = 250.0; // ns
       fTdb3 = 250.0; // ns
       EPwm1_DB = (Uint16)(fTdb * 0.1);
       EPwm2_DB = (Uint16)(fTdb2 * 0.1);
       EPwm3_DB = (Uint16)(fTdb3 * 0.1);
       fDutyCycle = 0.3;

       usPhase = (Uint16)(0.666666 * 0.5 * (float32)DC_DC_CONTROL_TBPRD);
       usPwm2Phase = usPhase; // Phase B Main
       usPwm3Phase = usPhase; // Phase C Main


       EPwm1Regs.TBPRD = (Uint16)(0.5 * (float32)DC_DC_CONTROL_TBPRD);                       // Set timer period
       EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
       EPwm1Regs.TBCTR = 0x0000;                     // Clear counter
       EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
       EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
       EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
       EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync Output Select: CTR = zero
   //    EPwm1Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
       EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
       EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
       EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
       EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
       EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
       EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
   //    EPwm1Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)CONTROL_TBPRD);
       EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;            // Set PWM1A on Zero
       EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
       EPwm1Regs.AQCTLB.bit.CAU = AQ_SET;          // Set PWM1A on Zero
       EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;
       EPwm1Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
       EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
       EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
       EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
       EPwm1Regs.DBRED.bit.DBRED = EPwm1_DB;
       EPwm1Regs.DBFED.bit.DBFED = EPwm1_DB;

       EPwm2Regs.TBPRD = (Uint16)(0.5  * (float32)DC_DC_CONTROL_TBPRD);                       // Set timer period
       EPwm2Regs.TBPHS.bit.TBPHS = usPwm2Phase;           // Phase is 0
       EPwm2Regs.TBCTR = 0x0000;                     // Clear counter
       EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
       EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
       EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN;               // Count down after the synchronization event
       EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
       EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
   //    EPwm2Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
       EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
       EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
       EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
       EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
       EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
       EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
   //    EPwm2Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)CONTROL_TBPRD);
       EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;            // Set PWM1A on Zero
       EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;
       EPwm2Regs.AQCTLB.bit.CAU = AQ_SET;          // Set PWM1A on Zero
       EPwm2Regs.AQCTLB.bit.CAD = AQ_CLEAR;
       EPwm2Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
       EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
       EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
       EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
       EPwm2Regs.DBRED.bit.DBRED = EPwm2_DB;
       EPwm2Regs.DBFED.bit.DBFED = EPwm2_DB;

       EPwm3Regs.TBPRD = (Uint16)(0.5 * (float32)DC_DC_CONTROL_TBPRD);                       // Set timer period
       EPwm3Regs.TBPHS.bit.TBPHS = usPwm3Phase;           // Phase is 0
       EPwm3Regs.TBCTR = 0x0000;                     // Clear counter
       EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
       EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
       EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP;               // Count down/up (0/1) after the synchronization event
       EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
       EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
   //    EPwm3Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
       EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
       EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
       EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
       EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
       EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
       EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
   //    EPwm3Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)CONTROL_TBPRD);
       EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;            // Set PWM1A on Zero
       EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;
       EPwm3Regs.AQCTLB.bit.CAU = AQ_SET;          // Set PWM1A on Zero
       EPwm3Regs.AQCTLB.bit.CAD = AQ_CLEAR;
       EPwm3Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
       EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
       EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
       EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
       EPwm3Regs.DBRED.bit.DBRED = EPwm3_DB;
       EPwm3Regs.DBFED.bit.DBFED = EPwm3_DB;



//    // Interrupt setting
//    EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;    // Select INT on Zero event
//    EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;          // Generate INT on 1st event
//    EPwm1Regs.ETSEL.bit.INTEN = 1;               // Enable INT



// PWM 4 used as ADC ISR
    EPwm4Regs.TBPRD = INV_PWM_TBPRD;                       // Set timer period
    EPwm4Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
    EPwm4Regs.TBCTR = 0x0000;                     // Clear counter
    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
    EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
    EPwm4Regs.TBCTL.bit.SYNCOSEL = 1; // Sync Output Select: CTR = zero
    EPwm4Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
//    EPwm11Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)INV_PWM_HALF_TBPRD);
    EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
    EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
    EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;            // Set PWM1A on Zero
    EPwm4Regs.AQCTLA.bit.CAD = AQ_SET;
    EPwm4Regs.AQCTLB.bit.CAU = AQ_SET;          // Set PWM1A on Zero
    EPwm4Regs.AQCTLB.bit.CAD = AQ_CLEAR;
    EPwm4Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
    EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm4Regs.DBRED.bit.DBRED = EPwm1_DB;
    EPwm4Regs.DBFED.bit.DBFED = EPwm1_DB;

    // ADC SOC
    EALLOW;
    EPwm4Regs.ETSEL.bit.SOCASEL = 1;   // Select SOC on Zero
    EPwm4Regs.ETSEL.bit.SOCAEN = 1;  //enable SOCA
    EPwm4Regs.ETPS.bit.SOCAPRD = ET_1ST;       // Generate pulse on ___ event
    EDIS;

/*    EPwm4Regs.ETSEL.bit.SOCAEN = 1;                 // Enable ePWM4 SOCA pulse
    EPwm4Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;      // SOCA from ePWM4 Zero event
    EPwm4Regs.ETPS.bit.SOCAPRD = ET_1ST;            // Trigger ePWM4 SOCA on every event

    EALLOW;

    PieVectTable.EPWM4_INT = &adca1_isr;         // Map CNTL Interrupt
    PieCtrlRegs.PIEIER3.bit.INTx4 = 1;          // PIE level enable, Grp3 / Int1, ePWM4
//    EPwm4Regs.CMPB = 50;                        // ISR trigger point
    EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;  // INT on CompareB-Up event
    EPwm4Regs.ETSEL.bit.INTEN = 1;              // Enable INT
    EPwm4Regs.ETPS.bit.INTPRD = ET_1ST;         // Generate INT on every 1st event
    EDIS;

    IER |= M_INT3;                              // Enable CPU INT3 connected to EPWM1-6 INTs:
    EINT;                                       // Enable Global interrupt INTM
    ERTM;   */                                    // Enable Global realtime interrupt DBGM


    // PWM modules for 3-phase inverter
    // EPWM 7,8, 9
    EPwm7Regs.TBPRD = INV_PWM_TBPRD;                       // Set timer period
    EPwm7Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
    EPwm7Regs.TBCTR = 0x0000;                     // Clear counter
    EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
    EPwm7Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
    EPwm7Regs.TBCTL.bit.SYNCOSEL = 1; // Sync Output Select: CTR = zero
    EPwm7Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
    EPwm7Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm7Regs.TBCTL.bit.CLKDIV = TB_DIV1;
//    EPwm11Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)INV_PWM_HALF_TBPRD);
    EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm7Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
    EPwm7Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
    EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR;            // Set PWM1A on Zero
    EPwm7Regs.AQCTLA.bit.CAD = AQ_SET;
    EPwm7Regs.AQCTLB.bit.CAU = AQ_SET;          // Set PWM1A on Zero
    EPwm7Regs.AQCTLB.bit.CAD = AQ_CLEAR;
    EPwm7Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
    EPwm7Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm7Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm7Regs.DBRED.bit.DBRED = EPwm1_DB;
    EPwm7Regs.DBFED.bit.DBFED = EPwm1_DB;

    EPwm8Regs.TBPRD = INV_PWM_TBPRD;                       // Set timer period
    EPwm8Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
    EPwm8Regs.TBCTR = 0x0000;                     // Clear counter
    EPwm8Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
    EPwm8Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
    EPwm8Regs.TBCTL.bit.SYNCOSEL = 1; // Sync Output Select: CTR = zero
    EPwm8Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
    EPwm8Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm8Regs.TBCTL.bit.CLKDIV = TB_DIV1;
//    EPwm12Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)INV_PWM_HALF_TBPRD);
    EPwm8Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm8Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm8Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
    EPwm8Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
    EPwm8Regs.AQCTLA.bit.CAU = AQ_CLEAR;            // Set PWM1A on Zero
    EPwm8Regs.AQCTLA.bit.CAD = AQ_SET;
    EPwm8Regs.AQCTLB.bit.CAU = AQ_SET;          // Set PWM1A on Zero
    EPwm8Regs.AQCTLB.bit.CAD = AQ_CLEAR;
    EPwm8Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
    EPwm8Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm8Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm8Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm8Regs.DBRED.bit.DBRED = EPwm1_DB;
    EPwm8Regs.DBFED.bit.DBFED = EPwm1_DB;

    EPwm9Regs.TBPRD = INV_PWM_TBPRD;                       // Set timer period
    EPwm9Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
    EPwm9Regs.TBCTR = 0x0000;                     // Clear counter
    EPwm9Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
    EPwm9Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
    EPwm9Regs.TBCTL.bit.SYNCOSEL = 1; // Sync Output Select: CTR = zero
    EPwm9Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
    EPwm9Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm9Regs.TBCTL.bit.CLKDIV = TB_DIV1;
//    EPwm9Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)INV_PWM_HALF_TBPRD);
    EPwm9Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm9Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm9Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
    EPwm9Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
    EPwm9Regs.AQCTLA.bit.CAU = AQ_CLEAR;            // Set PWM1A on Zero
    EPwm9Regs.AQCTLA.bit.CAD = AQ_SET;
    EPwm9Regs.AQCTLB.bit.CAU = AQ_SET;          // Set PWM1A on Zero
    EPwm9Regs.AQCTLB.bit.CAD = AQ_CLEAR;
    EPwm9Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
    EPwm9Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm9Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm9Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm9Regs.DBRED.bit.DBRED = EPwm1_DB;
    EPwm9Regs.DBFED.bit.DBFED = EPwm1_DB;
}



//
// ConfigureADC - Write ADC configurations and power up the ADC for both
//                ADC A and ADC B
//
void ConfigureADC(void)
{
    Uint16 acqps;

    EALLOW;

    //write configurations
    AdcaRegs.ADCCTL2.bit.PRESCALE = 2; //set ADCCLK divider to /2.0
    AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

    //Set pulse positions to late
    AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;

    //power up the ADC
    AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;

    //delay for 1ms to allow ADC time to power up
    DELAY_US(1000);

    EDIS;

    // Determine minimum acquisition window (in SYSCLKS) based on resolution
    if(ADC_RESOLUTION_12BIT == AdcaRegs.ADCCTL2.bit.RESOLUTION)
    {
        acqps = 14; //75ns
    }
    else //resolution is 16-bit
    {
        acqps = 63; //320ns
    }

    //Select the channels to convert and end of conversion flag
    EALLOW;
    AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0;  //SOC0 will convert pin A0
    AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
    AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = ADCTRIG; //ADCTRIG9 - ePWM3, ADCSOCA, ADCTRIG5 - ePWM1, ADCSOCA

    AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1;
    AdcaRegs.ADCSOC1CTL.bit.ACQPS = acqps;
    AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = ADCTRIG;

    AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2;
    AdcaRegs.ADCSOC2CTL.bit.ACQPS = acqps;
    AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = ADCTRIG;

    AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3;
    AdcaRegs.ADCSOC3CTL.bit.ACQPS = acqps;
    AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = ADCTRIG;

    AdcaRegs.ADCSOC4CTL.bit.CHSEL = 4;
    AdcaRegs.ADCSOC4CTL.bit.ACQPS = acqps;
    AdcaRegs.ADCSOC4CTL.bit.TRIGSEL = ADCTRIG;

    AdcaRegs.ADCSOC5CTL.bit.CHSEL = 5;
    AdcaRegs.ADCSOC5CTL.bit.ACQPS = acqps;
    AdcaRegs.ADCSOC5CTL.bit.TRIGSEL = ADCTRIG;

    AdcaRegs.ADCSOC6CTL.bit.CHSEL = 14;
    AdcaRegs.ADCSOC6CTL.bit.ACQPS = acqps;
    AdcaRegs.ADCSOC6CTL.bit.TRIGSEL = ADCTRIG;

    AdcaRegs.ADCSOC7CTL.bit.CHSEL = 15;
    AdcaRegs.ADCSOC7CTL.bit.ACQPS = acqps;
    AdcaRegs.ADCSOC7CTL.bit.TRIGSEL = ADCTRIG;

    AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 5; //end of SOCx will set INT1 flag
    AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1;   //enable INT1 flag
    AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
    EDIS;


    //For ADC-B


       EALLOW;

       //write configurations
       AdcbRegs.ADCCTL2.bit.PRESCALE = 2; //set ADCCLK divider to /2.0
       AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

       //Set pulse positions to late
       AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;

       //power up the ADC
       AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;

       //delay for 1ms to allow ADC time to power up
       DELAY_US(1000);

       EDIS;

       // Determine minimum acquisition window (in SYSCLKS) based on resolution
       if(ADC_RESOLUTION_12BIT == AdcbRegs.ADCCTL2.bit.RESOLUTION)
       {
           acqps = 14; //75ns
       }
       else //resolution is 16-bit
       {
           acqps = 63; //320ns
       }

       //Select the channels to convert and end of conversion flag
       EALLOW;
       AdcbRegs.ADCSOC0CTL.bit.CHSEL = 0;  //SOC0 will convert pin A0
       AdcbRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
       AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = ADCTRIG; //ADCTRIG9 - ePWM3, ADCSOCA, ADCTRIG5 - ePWM1, ADCSOCA

       AdcbRegs.ADCSOC1CTL.bit.CHSEL = 1;
       AdcbRegs.ADCSOC1CTL.bit.ACQPS = acqps;
       AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = ADCTRIG;

       AdcbRegs.ADCSOC2CTL.bit.CHSEL = 2;
       AdcbRegs.ADCSOC2CTL.bit.ACQPS = acqps;
       AdcbRegs.ADCSOC2CTL.bit.TRIGSEL = ADCTRIG;



       AdcbRegs.ADCINTSEL1N2.bit.INT1SEL = 5; //end of SOCx will set INT1 flag
       AdcbRegs.ADCINTSEL1N2.bit.INT1E = 1;   //enable INT1 flag
       AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
       EDIS;
}

void Shutdown(void)
{
    // software forced low on PWMA and PWMB
//    EPwm1Regs.AQCSFRC.bit.CSFA = 1;
//    EPwm1Regs.AQCSFRC.bit.CSFB = 1; // ***** THIS LINE HAS NO EFFECT ON PWMB *****
                                    // PWM1B STAYS HIGH
    EALLOW;
    GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0;
    GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0;
    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0;
    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0;
    GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 0;
    GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 0;
    GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0;
    GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0;
    GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0;
    GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0;
    GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0;
    GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0;
    GpioCtrlRegs.GPADIR.bit.GPIO0  = 1;   // output
    GpioCtrlRegs.GPADIR.bit.GPIO1  = 1;   // output
    GpioCtrlRegs.GPADIR.bit.GPIO2  = 1;   // output
    GpioCtrlRegs.GPADIR.bit.GPIO3  = 1;   // output
    GpioCtrlRegs.GPADIR.bit.GPIO4  = 1;   // output
    GpioCtrlRegs.GPADIR.bit.GPIO5  = 1;   // output
    GpioCtrlRegs.GPADIR.bit.GPIO6  = 1;   // output
    GpioCtrlRegs.GPADIR.bit.GPIO7  = 1;   // output
    GpioCtrlRegs.GPADIR.bit.GPIO8  = 1;   // output
    GpioCtrlRegs.GPADIR.bit.GPIO9  = 1;   // output
    GpioCtrlRegs.GPADIR.bit.GPIO10 = 1;   // output
    GpioCtrlRegs.GPADIR.bit.GPIO11 = 1;   // output
    EDIS;
    GpioDataRegs.GPACLEAR.bit.GPIO0 = 1;
    GpioDataRegs.GPACLEAR.bit.GPIO1 = 1;
    GpioDataRegs.GPACLEAR.bit.GPIO2 = 1;
    GpioDataRegs.GPACLEAR.bit.GPIO3 = 1;
    GpioDataRegs.GPACLEAR.bit.GPIO4 = 1;
    GpioDataRegs.GPACLEAR.bit.GPIO5 = 1;
    GpioDataRegs.GPACLEAR.bit.GPIO6 = 1;
    GpioDataRegs.GPACLEAR.bit.GPIO7 = 1;
    GpioDataRegs.GPACLEAR.bit.GPIO8 = 1;
    GpioDataRegs.GPACLEAR.bit.GPIO9 = 1;
    GpioDataRegs.GPACLEAR.bit.GPIO10 = 1;
    GpioDataRegs.GPACLEAR.bit.GPIO11 = 1;

    usRunState = FAULT;
    usResumePWM = 0;
    fDutyCycle = 0.0;
    fDutyCycle2 = 0.0;
    fDutyCycle3 = 0.0;
    EPwm1_CMP = 0;
    EPwm2_CMP = 0;
    EPwm3_CMP = 0;

    fVerr = 0.0;
    fInt2 = 0.0;
//    fVoltCtrl = 0.0;

    fIerrA = 0.0;
    fIerrB = 0.0;
    fIerrC = 0.0;
    fIntA  = 0.0;
    fIntB  = 0.0;
    fIntC  = 0.0;
    fCurrCtrlA = 0.0;
    fCurrCtrlB = 0.0;
    fCurrCtrlC = 0.0;
}

//
// End of file
//