TMS320F28035: The first pulse width of epwm is not controlled

Green Deng

Part Number: TMS320F28035

Dear team:

One of my customers uses six step commutation method to control BLDC, but the first pulse of each commutation is not controlled, which is quite different from the comparison value set by him, resulting in excessive current.

The following are the waveforms and PWM program:

Sometimes the first pulse width is different：

Sometimes, the following superposition will appear:

PWM configuration：


\
EALLOW; \
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; \
EDIS; \
\
/* Init Timer-Base Period Register for EPWM1-EPWM3*/ \
EPwm1Regs.TBPRD = v.PWMprd; \
EPwm2Regs.TBPRD = v.PWMprd; \
EPwm3Regs.TBPRD = v.PWMprd; \
\
/* Init Timer-Base Counter Register for EPWM1-EPWM3*/ \
EPwm1Regs.TBCTR = 0x0000; \
EPwm2Regs.TBCTR = 0x0000; \
EPwm3Regs.TBCTR = 0x0000; \
\
/* Init Compare Register for EPWM1-EPWM3 to 50% duty cycle */ \
EPwm1Regs.CMPA.half.CMPA = v.PWMprd/2; \
EPwm2Regs.CMPA.half.CMPA = v.PWMprd/2; \
EPwm3Regs.CMPA.half.CMPA = v.PWMprd/2; \
\
/* Init Timer-Base Phase Register for EPWM1-EPWM3*/ \
EPwm1Regs.TBPHS.half.TBPHS = 0; \
EPwm2Regs.TBPHS.half.TBPHS = 0; \
EPwm3Regs.TBPHS.half.TBPHS = 0; \
\
/* Init Timer-Base Control Register for EPWM1-EPWM3*/ \
EPwm1Regs.TBCTL.all = PWM_CNTL_INIT_STATE; \
EPwm2Regs.TBCTL.all = PWM_CNTL_INIT_STATE; \
EPwm3Regs.TBCTL.all = PWM_CNTL_INIT_STATE; \
\
/* Setup Sync*/ \
EPwm3Regs.TBCTL.bit.SYNCOSEL = 1; \
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0; \
EPwm1Regs.TBCTL.bit.SYNCOSEL = 0; \
\
/* Allow each timer to be sync'ed*/ \
EPwm3Regs.TBCTL.bit.PHSEN = 0; \
EPwm2Regs.TBCTL.bit.PHSEN = 1; \
EPwm1Regs.TBCTL.bit.PHSEN = 1; \
\
/* Set count dir after sync event*/ \
EPwm3Regs.TBCTL.bit.PHSDIR = 0; \
EPwm2Regs.TBCTL.bit.PHSDIR = 1; \
EPwm1Regs.TBCTL.bit.PHSDIR = 1; \
\
/* Init Compare Control Register for EPWM1-EPWM3 */ \
EPwm1Regs.CMPCTL.all = BLDCPWM_CMPCTL_INIT_STATE; \
EPwm2Regs.CMPCTL.all = BLDCPWM_CMPCTL_INIT_STATE; \
EPwm3Regs.CMPCTL.all = BLDCPWM_CMPCTL_INIT_STATE; \
\
/* Init Action Qualifier Output A Register for EPWM1-EPWM3*/ \
EPwm1Regs.AQCTLA.all = PWM_CNTL_AQCTLA_INIT_STATE_4; \
EPwm2Regs.AQCTLA.all = PWM_CNTL_AQCTLA_INIT_STATE_4; \
EPwm3Regs.AQCTLA.all = PWM_CNTL_AQCTLA_INIT_STATE_4; \
\
/* Init Dead-Band Generator Control Register for EPWM1-EPWM3*/ \
EPwm1Regs.DBCTL.all = DBCTL_INIT_STATE; \
EPwm2Regs.DBCTL.all = DBCTL_INIT_STATE; \
EPwm3Regs.DBCTL.all = DBCTL_INIT_STATE; \
\
/* Init Dead-Band Generator for EPWM1-EPWM3*/ \
EPwm1Regs.DBFED = DBCNT_INIT_STATE; \
EPwm1Regs.DBRED = DBCNT_INIT_STATE; \
EPwm2Regs.DBFED = DBCNT_INIT_STATE; \
EPwm2Regs.DBRED = DBCNT_INIT_STATE; \
EPwm3Regs.DBFED = DBCNT_INIT_STATE; \
EPwm3Regs.DBRED = DBCNT_INIT_STATE; \
\
/* Init PWM Chopper Control Register for EPWM1-EPWM3*/ \
EPwm1Regs.PCCTL.all = BLDCPWM_PCCTL_INIT_STATE; \
EPwm2Regs.PCCTL.all = BLDCPWM_PCCTL_INIT_STATE; \
EPwm3Regs.PCCTL.all = BLDCPWM_PCCTL_INIT_STATE; \
\
\

其中

#define PWM_CNTL_INIT_STATE ( FREE_RUN_FLAG + \
PRDLD_SHADOW + \
TIMER_CNT_UPDN + \
HSPCLKDIV_PRESCALE_X_1 + \
CLKDIV_PRESCALE_X_1 + \
PHSDIR_CNT_UP + \
CNTLD_DISABLE )

#define BLDCPWM_CMPCTL_INIT_STATE ( LOADAMODE_ZRO + \
LOADBMODE_ZRO + \
SHDWAMODE_IMMEDIATE + \
SHDWBMODE_IMMEDIATE )

#define  PWM_CNTL_AQCTLA_INIT_STATE_4   ( PRD_SET + CAU_CLEAR )

#define DBCTL_INIT_STATE  (BP_ENABLE + POLSEL_ACTIVE_HI_CMP)

#define  BLDCPWM_PCCTL_INIT_STATE  CHPEN_DISABLE

换向部分函数：

#define MOD6CNTDIR_MACRO(v) \
\
if (v.TrigInput > 0) \
{ \
if(v.Counter == 5) \
{ \
v.Counter = 0; \
data=data+1; \
datasa=1; \
EPwm1Regs.TBCTR = 3000; \
EPwm2Regs.TBCTR = 3000; \
EPwm3Regs.TBCTR = 3000; \
} \
else \
{ \
v.Counter++; \
EPwm1Regs.TBCTR = 3000; \
EPwm2Regs.TBCTR = 3000; \
EPwm3Regs.TBCTR = 3000; \
} \
}

over 4 years ago

0 Cody Watkins over 4 years ago

TI__Mastermind 42195 points

Green,

First figure:

Does this only happen at startup, or is the customer disabling and reenabling the PWM output when they see this? If they are disabling and enabling the PWM output during runtime, how are they doing this?

When does the customer select the PWM output mux option on the GPIO buffer? Does this happen before or after the setup code above? When leaving some boundary conditions like 0% duty cycle it is necessary to use the software force in the Action Qualifier sub module.

Second figure:

In your second figure I cannot tell what each channel corresponds to, or what the customer was wanting to output. Please detail this better and perhaps I can help.

Regards,
Cody

0 richard wang over 4 years ago

DEAR Cody：

Thank you for the reply！

this doesn't not only happen at starup,it happens at each commutation which the LOW output turn to the pwm signal.

this happens after the setup code above and i had use the software force in the Action Qualifier sub module.

the next codes are the two steps of six steps commutation method

#define PWM_CNTL_MACRO_3(v,ch1,ch2,ch3) /* */\

_iq iqPosDuty = _IQ(0.5); /* */\

Uint16 uiPosDuty = 0; /* */\

Uint16 uiNegDuty = 0; /* */\

/* */\

iqPosDuty = _IQmpy(v.Duty, _IQ(1.0)); /* */\

uiPosDuty = (Uint16) ((_IQ18mpy((_iq)v.PWMprd<<18, _IQtoIQ18(iqPosDuty))) >> 18); /* */\

uiNegDuty = v.PWMprd - uiPosDuty; /* */\

switch (v.State) /* */\

{ /* */\

/* State s1: current flows to motor windings from phase A->B, de-energized phase = C */\

case 0: /* */\

EALLOW; /* */\

EPwm3Regs.CMPA.half.CMPA = uiNegDuty; /*v.PWMprd */\

EPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE ; \

EPwm1Regs.AQCSFRC.bit.CSFA = 1; /* */\

EPwm1Regs.AQCSFRC.bit.CSFB = 1; /* */\

EPwm2Regs.DBCTL.bit.OUT_MODE = DB_DISABLE ; \

EPwm2Regs.AQCSFRC.bit.CSFA = 2; /* */\

EPwm2Regs.AQCSFRC.bit.CSFB = 1; /* */\

EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE ; \

EPwm3Regs.AQCSFRC.bit.CSFA = 0; /* */\

EPwm3Regs.AQCSFRC.bit.CSFB = 0; /* */\

EDIS; /* */\

break; /* */\

/* */\

/* State s2: current flows to motor windings from phase A->C, de-energized phase = B */\

case 1: /* */\

EALLOW; /* */\

EPwm1Regs.CMPA.half.CMPA = uiPosDuty; /* 0 */\

EPwm2Regs.DBCTL.bit.OUT_MODE = DB_DISABLE ; \

EPwm2Regs.AQCSFRC.bit.CSFA = 1; /* */\

EPwm2Regs.AQCSFRC.bit.CSFB = 1; /* */\

EPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE ; \

EPwm3Regs.AQCSFRC.bit.CSFA = 1; /* */\

EPwm3Regs.AQCSFRC.bit.CSFB = 2; /* */\

EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE ; \

EPwm1Regs.AQCSFRC.bit.CSFA = 0; /* */\

EPwm1Regs.AQCSFRC.bit.CSFB = 0; /* */\

EDIS; /* */\

break; /* */\

Hope for the answer, thank you ~

0 Cody Watkins over 4 years ago in reply to richard wang

TI__Mastermind 42195 points

Richard,

Are you using Up-down count mode? I suspect that you are running into the issue called out in this document. https://www.ti.com/lit/pdf/spraai1

For F28035, the PWM will not miss CMPA = 0,so the "non-zero to CMPA=0" workaround can be ignored. However the workaround described in the document is still required when going from CMPA=0 to a non-zero value.

Please evaluate the document and see if this is your issue.

Regards,
Cody

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TMS320F28035: The first pulse width of epwm is not controlled