Frequent Questions

  • [FAQ] PLLATINUMSIM-SW: PLL Training Material

    Part Number: PLLATINUMSIM-SW Attached is a detailed training on PLL Theory PLL Fundamentals Full Training (Public).pdf

  • [FAQ] LMK5B33216: How to choose the loop bandwidth for your PLL

    Part Number: LMK5B33216 Here's some information on choosing a loop bandwidth for your PLL to optimize noise performance. The presentation starts with some general theory on noise and PLLs, discusses how to pick loop bandwidth for a "PLL/VCO optimized…

  • [FAQ] TDA4VEN-Q1: TIDL back port from 10.x or 11.x to higher version

    Part Number: TDA4VEN-Q1 Other Parts Discussed in Thread: AM68A , AM69A , AM67A , TDA4VH Get the desired version of tidl firmware: Download according to edgeai-tidl-tools script: https://github.com/TexasInstruments/edgeai-tidl-tools/blob/master…

  • [FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM625SIP - Collaterals for reference during different phases of custom board design, self-review and bring-up

    Part Number: AM625 Other Parts Discussed in Thread: AM623 , , , AM620-Q1 , , SK-AM62B-P1 , SK-AM62-LP , SK-AM62B , SK-AM62-SIP , AM62D-Q1 , AM62X-PET-CALC Hi TI Experts, I am starting a new project and want to use Sitara processor in the design. Can…

  • [FAQ] TDA4VM: How to do IPC echo test example on TDA4VH/VM

    Part Number: TDA4VM Other Parts Discussed in Thread: TDA4VH Hi Team, How can I build and run IPC Echo test example on TDA4VH boards?

  • [FAQ] AWR2E44PEVM: [FAQ] AWR2E44P: Antenna Calibrations

    Part Number: AWR2E44PEVM The following are the steps to calibrate the LOP antenna for the AWR2E44PEVM. Flash the board with the mmw app image present in the latest SDK. Example Path: C:\ti\mmwave_mcuplus_sdk_04_07_01_04\mmwave_mcuplus_sdk_04_07_01_04…

  • [FAQ] AM625 / AM623 / AM625-Q1 / AM620-Q1 / AM62L / AM62A / AM62P / AM62D-Q1 / AM64x / AM243x Custom board hardware design - Processor pin mapping and SK board connections (Supply rail, Capacitors and ferrites)

    Part Number: AM625 Other Parts Discussed in Thread: TMDS64EVM , SK-AM64B , TMDS62LEVM , SK-AM62B-P1 , SK-AM62-LP , SK-AM62B , SK-AM62A-LP , AUDIO-AM62D-EVM , SK-AM62P-LP , SK-AM62-SIP Hi TI Experts, Please provide the SOC power pin mapping and connection…

  • [FAQ] CC2340R5: Issues with CC2340R53 and SmartRF Studio 1.3.0 and 1.3.1

    Part Number: CC2340R5 If you are working with SmartRF Studio 8 versions 1.3.0 and 1.3.1 AND a CC2340R53 device, please note that SmartRF Studio's Radio Control Window might fail to detect the board. In other words, you will see the scenario below…

  • [FAQ] UCC27735-Q1: How can I build a circuit to generate a negative turn-off voltage?

    Part Number: UCC27735-Q1 Other Parts Discussed in Thread: UCC27624 , UCC27735 , UCC27301A , UCC27734 In Fundamentals of Gate Drivers section 6, there is a description of how to use AC coupling to create a negative gate voltage. Wide-bandgap devices…

  • [FAQ] J7200XSOMXEVM: Unable to connect to cluster-1 of MCU R5F and Main R5F in No-boot mode from CCS debugger

    Part Number: J7200XSOMXEVM Other Parts Discussed in Thread: DRA821 After loading the Gel script as described in PSDK RTOS in No Boot Mode, I am unable to connect to the MCU_R5F_0_1 and Main_R5F_0_1 cores.

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