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TMS320F28379D: Shadow of OUT_MODE and OUTSWAP bits in DBCTL

Thomas Wappler
Intellectual 395 points
Part Number: TMS320F28379D

Hi,

I wanted use the OUTSWAP feature with shadow of the deadband module of my device. But it seems that the OUTSWAP bits are not shadows while the others are.
Should this bitfield be shadowed?

For testing run a ISR at CTR=PRD (up-down counting mode), while reload of DBCTL is configured to CTR=0. So I would expect that the signals do not change when the ISR is executed.

The dead band generator is configured as shown in the following link, but S3 is set to one.

The delays are set to zero, so effectivly ePWM1A is passed to the point RED and ePWM1B is inverted and passed  to FED.

ePWM1A has a smaler duty cycle that ePWM1B to visualise the signal.

Where the left cursors sits this is executed:

//          EPwm1Regs.DBCTL.bit.OUTSWAP = 0x3; (swap outputs)
//          EPwm1Regs.DBCTL.bit.OUT_MODE = 0x3; (enable inversion of B)
          EPwm1Regs.DBCTL.all = 12331;
and at the right cursor:

//          EPwm1Regs.DBCTL.bit.OUTSWAP = 0x0; (unswap outputs)
//          EPwm1Regs.DBCTL.bit.OUT_MODE = 0x0; (disable inversion of B=
          EPwm1Regs.DBCTL.all = 40;

As you can see on the scope the outputs are swaped immediately at the cursor, while the inversion of B occurs 50us later at CTR=zero.

CH7 =B
CH6 = A


Thanks,
Thomas.

  • 0
    Intellectual 395 points

    Sorry.

    That line:

    The dead band generator is configured as shown in the following link, but S3 is set to one.

    should say:

    The dead band generator is configured as shown in the following link:

  • 0 in reply to Thomas Wappler
    TI__Genius 10820 points
    Hi Thomas,

    This is interesting. Are you using up-count mode? Can you share your action qualifier settings too? I am just trying to ascertain where the CTR = 0 event might be occurring on the waveform.

    Thanks.
    Hrishi
  • 0 in reply to Hrishi Nene
    Intellectual 395 points

    Hi Hrishi,

    I used up-down counting mode.
    CTR = 0 alligns with the scope grid.

    The pulse in CH0 (bottom left corner) is a GPIO which ist set and reset in a IRQ at CTR=PRD.

    here are my AQ settings:

        EPwm1Regs.AQCTLA.all = 0;
        EPwm1Regs.AQCTLA.bit.CAU = 0x1; // clear
        EPwm1Regs.AQCTLA.bit.CAD = 0x2; // set

        EPwm1Regs.AQCTLB.all = 0;
        EPwm1Regs.AQCTLB.bit.CBU = 0x1; // clear
        EPwm1Regs.AQCTLB.bit.CBD = 0x2; // set


    Here are also the settings in DBCTL and DBCTL2:

        // activate shadow mode for DBCTL
        EPwm1Regs.DBCTL2.bit.SHDWDBCTLMODE = 0x1;
        // reload on CTR = 0
        EPwm1Regs.DBCTL2.bit.LOADDBCTLMODE = 0x0;

        EPwm1Regs.DBRED.bit.DBRED = 0;  // Dead-Band Generator Rising Edge Delay Count Register
        EPwm1Regs.DBFED.bit.DBFED = 0;  // Dead-Band Generator Falling Edge Delay Count Register

        EPwm1Regs.DBCTL.bit.OUT_MODE = 0x3;
        EPwm1Regs.DBCTL.bit.POLSEL = 0x2;
        EPwm1Regs.DBCTL.bit.IN_MODE = 0x2;
        EPwm1Regs.DBCTL.bit.OUTSWAP = 0x0;
        EPwm1Regs.DBCTL.bit.DEDB_MODE = 0x0;

    Thanks,

    Thomas.

    TMS320F28379D: Shadow of OUT_MODE and OUTSWAP bits in DBCTL

  • 0 in reply to Thomas Wappler
    Intellectual 395 points

    Hi,

    are there any news on this topic?

    Meanwhile I use the AQ settings to achive the output swap. That works, but may involve other trouble.

    Here is the relevant part of the reference manual:

    The DBCTL register can be shadowed. The shadow mode for DBCTL is enabled by setting the
    DBCTL2[SHDWDBCTLMODE] bit. If the shadow register is enabled then the content of the shadow
    register is transferred to the active register on one of the following events as specified by the
    DBCTL2[LOADDBCTLMODE] register bit:
    • CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD)
    • CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)
    • Both CTR = PRD and CTR = Zero

    Best regards,

    Thomas.

  • 0 in reply to Thomas Wappler
    TI__Genius 10820 points

    Hi Thomas,

    Sorry for the delay. Here's what I got back from design:

    Note: Shadowing is applicable for bits [5:0] of DBCTL. Other bits are not affected by shadow load operation. 

    This means that the behavior you've reported is expected.

    Typically it is not recommended to swap the two outputs during operation. If it must be done, I recommend implementing it during a 'quiet' time of the operation when there's no switching or when the outputs are in the same state.

    I hope this helps.

    Hrishi

  • 0 in reply to Hrishi Nene
    Intellectual 395 points

    Hi Hrishi,

    thanks for your answer.

    Best regards,

    Thomas.

  • 0 in reply to Thomas Wappler
    Intellectual 395 points

    Hi Hrishi,

    I just came over exactly the same problem like Mr. Peng in this post from 2016:

    Shadow register AQCTLA and AQCTLA2 in TMS320F2837xS Technical Reference Manual on P1578-P1580 - C2000...

    e2e.ti.com
    Question1: Does AQCTLA2 register have shadow register? it's clear that AQCTLA register have shadow register which can be configured in AQCTL register. AQCTLA2

    I would really apreciate if TI would update the shadowing of DBCTL and AQCTLy2 y=A/B in the reference manual.

    Best regards,
    Thomas.

  • 0 in reply to Thomas Wappler
    TI__Genius 10820 points

    Hi Thomas,

    Thank you for this feedback. I will add it to our document update list if it's not already there.

    Hrishi