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I had an earlier problem in CCS 9 (or more specifically the GCC includes provided with this) where ISR's in a MSP430FR5964 were being placed in RAM rather than ROM. This was due to a missing .lowtext SECTION definition in the .ld files for the 5964 and a number of other MSP430 processors.
I've just been in the process of upgrading to CCS 10.4, and can confirm that the problem still exists with this release. I've checked the 5964, 5994 and a few of the other processors mentioned, and it appears to impact the same group of processors.
As previously, the fix is relatively simply, and simply involves adding .lowtext to the sections collected for inclusion in ROM (or FRAM in this case). I've simply picked the .ld from a processor that correctly includes the definition, and modified the msp430fr5964.ld to follow the same pattern.
Nothing to be done here - it's just for posterity if someone else trips over this. The issue is already raised from CCS 9. As far as I know, it only impacts the GCC toolchain.
Andrew
Andrew,
Thanks for the feedback. I will pass this along to the software team to look into.
This issue appears to have been fixed in MSP430-GCC 9.3.1.2. After installing the latest version from https://www.ti.com/tool/download/MSP430-GCC-OPENSOURCE and copy ~/ti/msp430-gcc/include/msp430fr5994.ld to overwrite the msp430fr5994.ld file in my project, interrupt handlers are working fine again.
~/ti/msp430-gcc/Revisions_Header.txt mentions "Fix missing lowtext section for GCC linker files" in bug fixes. I guess that is the key change.
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